Research On Encoder And Decoder Of QC-LDPC Based On FPGA

In recent years, with the continuous development of communicationtechnology, low density parity check (LDPC) code has been applied more andmore. Low density parity check code has some features, such as tiny shannonlimit gap、extremely efficient ability of compiled code execution, etc. Comparedwith the random LDPC code, quasi-cyclic code structure is more flexible, andhardware implementation is more outstanding. It can operate according to thestructural characteristics of the parallel operation, thus it gradually becomes hotspot in research field.As the change of channel, the encoder and decoder that only support singlecode-rate LDPC cannot have satisfied the development of moderncommunication applications, and in the actual communication system themulti-parameter QC-LDPC code is gradually regarded as the channel decodingscheme. In this paper, based on the problems that the current QC-LDPC codedecoder hardware structure is not flexible and decoding delay is larger,an encoderand decoder which can support multi-parameter is studied, and it has a lowercomplexity.The QC-LDPC encoding and decoding algorithm that facilitate the FPGAimplementation is proposed in this paper. In the aspect of encoding algorithm,coding algorithm based on shift register mode is presented according to thecomprehensive consideration of complexity and encoding throughput rate and soon. In the aspect of decoding algorithm, an improved algorithm is studied basedon the Min-sum algorithm, and we find its better algorithm performance andlower complexity by simulation.According to the given encoding and decoding algorithm,encoder anddecoder scheme based on FPGA is finished.The check code and data storage module is optimized, the multi-parameter of QC-LDPC encoder is implementatedby using simple shift register.The external information storage solution isreasonable planned through the adoption of part of design of parallel structure,ping-pong operation, pipelining and other works is adopted in the moduleoperation, which improves the throughput of decoder, and the consumption ofhardware resources is similar to single parameter. The function and design ofeach module have been finished, and state transition diagram and RTL view ofthe module have been designed. Verilog language is used to describe hardwarestructure of the functional module,and Modelsim timing simulation diagram isgiven,which is used to verify every module.The whole system is simulated and performance evaluted, the effectivenessof the design structure is concluded.