FPGA-based QC-LDPC Layered Decoder Design And Coded-MIMO Performance Studies

Gallager proposed LDPC codes in1962. Mackey and Neal rediscovered it in1963and made theresearch of LDPC codes into a new phase. Due to its performance is the closest approach to theShannon limit and it can be decoded efficiently, LDPC codes have become a hot topic in the channelcoding field and the support object of the next generation of the mobile communication. Because ofits superior performance, it has been applied in areas of satellite communications, the next generationof wireless communication, magnetic memory, network packet transmission, etc.With the theoretical development of the LDPC codes, the hardware implementation has alsodeveloped rapidly, but the randomness in the structure of LDPC codes makes the hardwareimplementation difficult. After QC-LDPC codes being proposed, it’s quasi-cyclic structure can bemade full use, which achieves a balance between decoding throughput and hardware resourcesconsumption. Therefore QC-LDPC codes are more suitable for hardware implementation andpromotion.The method of the check matrix construction and the encoding and decoding algorithm based onthe layered decoding structure of QC-LDPC will be introduced. Taking use of circle-cancelconstruction and applying the improved method to construct the check matrix can make theperformance of QC-LDPC more prior and rapid encoding. In terms of decoding algorithm, thenormalized min-sum algorithm which only involves the operation of addition and comparison can beused, and the correction factor of NMSA can be determined via software simulation.Due to MIMO systems can effectively improve the spectrum efficiency of wirelesscommunication system by taking advantage of the signal space and using the spatial degrees offreedom provided by multiple transmit antennas and multiple receive antennas, which can enhance thetransmission rate and improve the communication quality. MIMO technology has become a hot topicin the future communication area. MIMO technology and QC-LDPC codes are magnitude boundtogether to form concatenated QC-LDPC/MIMO systems, which can achieve anti-interference andreduce the noise efficiently.Finaly, the hardware program was finished with Verilog language to implement the QC-LDPClayered decoder on FPGA. Based on the layered decoding structure, the design for2048-length,34-rate,(3,12) non-layered QC-LDPC codes can be completed under Strtix II EP2S60F484C3 FPGA of Altera, Inc. When the clock frequency is90MHz and the maximum iteration number is5, thedecoding throughput can reach93.85Mbps.