On The FPGA Design And Implementation Of The IEEE802.16e LDPC Decoder

Since being rediscovered in 1990s, LDPC codes have attracted people's attention and have become another research focus of channel coding filed after Turbo codes because of their capacity approaching error correction capability and the advantages of low decoding complexity and high decoding throughput. Today, LDPC codes have been widely applied in different communication systems such as DVB-S2, CMMB and Wi-Fi. LDPC codes are the optional channel coding scheme in the IEEE 802.16e standard. With the progress in the LDPC codes in recent years, there is a high probability that LDPC codes will be utilized in the future fourth generation mobile communication systems. In this paper, the FPGA design and implementation of the LDPC decoder for the IEEE 802.16e standard is highlighted, and the thesis is organized as follows.Firstly, the error-correction performance and decoding complexity of several soft-decision decoding algorithms are presented to compare the achived reliability and the implementation complexity. Finally, it is shown that, the Offset Min-Sum algorithm is a reasonable choice for the hardware implementation due to its realiability and low implementation complexity. Meanwhile, it is validated that, the offset factorβ=0.125 and the fixed-point form of (6:3) is highly recommended throughput the software simulations.Secondly, after the comparison of the implementation architecture of some known LDPC decoder codecs, the partially parallel architecture, which meets with the quasi-cyclic LDPC decoding nature, is adopted as the basic decoding architecture. Moreover, some improved methods are presented to make the partially parallel decoding structure to support not only all of the 6 kinds of code rate and 19 kinds of code length specified by the IEEE 802.16e standard, but also support the consecutive block data decoding processing and the early iteration stopping criterion.Thirdly, the LDPC design and implementation is validated on the ModelSim-based functional simulation test platform, and then synthesized on the StratixⅡGX family FPGA devices by using QuartusⅡsoftware kit. And the synthesis results show that, the realized decoder supports a throughput up to more than 95Mbps for the fixed 15 iterations at the clock frequency of 150MHz, which meets the requirements of the IEEE 802.16e standard.Finally, the decoder realized in this paper is compared with other LDPC decoders reported in the literature, and the comparison results show that, with some paid cost in the hardware resource consumption (in particular the memory recource), this implemented LDPC decoder in this thesis is a general purpose codec, which is ablo to support all code rate and code size in IEEE 802.16e with a satisfactory decoding throughput. Meanwhile it could be improved significantly in terms of the achived decoding throughput performance if high speed readable-writable memory chips could be utilized.