Efficient FPGA Implementation Of LDPC Encoder And Decoder In NGB-W System

Low Density Parity Check code(LDPC) is a kind of linear block code, which is defined by a sparse parity check matrix. Its decoding performance is the most close to the Shannon limit of the known coding and decoding technology, so the code has a very broad application prospects.Next Generation Broadcast Network Wireless systerm(NGB-W) provides a variety of services, such as voice, video and data connection, to achieve the national "Triple-play" as the strategic target, to promote the transformation of traditional media and the development of new media, to promote the rapid development of China's information service industry. However, the digital TV broadcast channel is a kind of long delay and frequency selective multipath fading channel, and the error in the channel transmission can be effectively corrected by LDPC code with the powerful error correcting capability. At the same time, NGB-W system using BCH(outside) codes and LDPC(inner) codes as concatenated coding scheme, has the very good error correcting capability.This thesis is based on the Next Generation Broadcast Network Wireless systerm projects, the main target is to implement the LDPC encoder and decoder with low complexity and high throughput. In this thesis from the basic principle of the key technology LDPC codes is proceed, the LDPC code structure and several methods of constructing(Gallager construction method, PEG construction method and permutation matrix construction method) are analyzed, and LDPC Encoding and decoding algorithm(BP algorithm and Min-sum algorithm) are studied. Through the study found that most of the decoding algorithm of LDPC codes is based on(normalized or offset) Min-sum algorithm, although all have good performance, but each iteration contains two scanning calculation process, horizontal and vertical scanning, and implementation is more complex. Considering all the factors, this thesis presents suitable Single-scan Min-sum algorithm for NGB-W system, to complete the horizontal scanning and vertical scanning in one scan calculation process, reducing the use of storage unit, simplifying the information transfer relation between variable and check nodes, which simplifies the hardware implementation complexity and can achieve the same effect of decoding. According to the structural characteristics of LDPC codes, the structure model of the encoder and decoder is analyzed and determined.In the decoder, the Single-scan Min-sum algorithm are combined with the layered structure to improve the convergence rate.Top-down design method are used in the process of hardware implementation, ping-pong operation, running water and other engineering design techniques are also be used, Verilog HDL language are used to complete the RTL level circuit design of encoder and decoder. The design is simulated and verified by the combination of Modelsim and Quartus II platform. Finally, the LDPC encoder and decoder are verified on the Altera Stratix V series FPGA platform, and the system can work stably and normally. NGB-W system works in MIMO mode, the frequency of decoder can reach 130 Mhz, the throughput of 3/4 code rate data can reach 75 Mbps. The design has reached requirements of NGB-W system.