Research On The High-effective LDPC Decoder Based On FPGA Platform

ABSTRACT:As a Shannon-limit approaching coding technique, low-density parity-check (LDPC) codes have been widely accepted in the high speed communication system. In the high speed communication system, a high throughput decoder is indispensible, which result in the hardware implementation of LDPC decoder being a hotspot in the research area. As a programmable and high speed device, the FPGA become the first choice of the LDPC decoder implementation platform.This paper start with doing a research on the LDPC soft decode algorithms, and we choose the MS algorithm as the decoding algorithm to be implemented on our decoder considering the performance and complexity of these algorithms. Based on MS decode algorithm two kinds of LDPC decoder were proposed.The first one is a low-consumption configurable LDPC decoder, it can be configured to fit all kinds of LDPC codes. This decoder use less resources through optimizing the method of messages packaging, of which the pipeline structure guarantees no lose of throughput. It was applied in the random and QC-LDPC codes, in comparison with the partial decoders previously implemented, the proposed decoder significantly reduces the number of block RAMs used for extrinsic messages by half.The other one is a QC-LDPC decoder, it gets a high-throughput by performing CN (check node) and VN (variable node) updating simultaneously, which eliminates the waiting time between CN and VN updating. In this paper, the LDPC code of1/2code rate in IEEE802.11ad standard was selected to be emulated in BPSK modulation mode. It got a throughput about200M with100MHz clock frequency. The result shows that it can get a throughput40%higher than the partial decoder, while the same RAM count as the partial decoder is used.For the purpose of verifying the LDPC decoder, a LDPC simulation platform was designed, which contains LDPC encoder and decoder, AWGN channel simulation. These modules were tested on the Xilinx Spartan-6FPGA platform. This paper presents the BER performance of the LDPC code achieved on the simulation platform, which is the same as matlab simulation.