Design And Implementation Of Performance Counters In An OpenRISC Processor

OpenRISC is an open source hardware RISC CPU designed by OpenCores released under the GNU Lesser General Public License. The OpenCores team implemented the design in the verilog hardware description language. The OpenRISC processor can be implemented either in an ASIC system or in a FPGA system.Performance counters are a set of special-purpose registers built in modern processors to measure events that occur during program execution. Advanced users often rely on those counters to conduct low-level performance analysis or tuning. By analysing the real-time hardware running information they can estimate the performance of the processor and improve the execution efficiency of software programs.In this paper, we try a design flow as investigation, specification definition, hardware design coding, simulation, chipscope debugging and JTAG remote debugging to integrate the Performance Counters Unit (PCU) into OpenRISC 1200 processor core. The PCU can be accessed either as JTAG remote debugging or as special-purpose register Read/Write. An SOPC system is built based on this new processor core. On the FPGA implementation of the new processor core, applications are executed on this new processor core and the functions of performance counters are verified.Then by modifying the bus system and I/O interface of the OpenRISC processor we build a dual-core system. Some test has been done in this system to verify the performance counters.