On-chip Communication Of Embedded Heterogeneous Multi-core Architecture

Along with the development of the semiconductor manufacturing and the in-depth research of the processor architecture, the heterogeneous multi-core processor will be widely used in the embedded system, while the on-chip communication is one of the critical points in heterogeneous multi-core architecture design.Currently, on-chip communication design has achieved some production. However, there are still lots of problems need to be solved, such as the cooperation mode of on-chip cores and the efficient sharing of on-chip communication path. While in the domain of embedded heterougeneous multi-core processor, different kinds of cores have different requirements, and the cost of design and implement of processor is strictly confined. Therefore, on-chip communication design should be further developed to achieve better performance.In this paper, we focused on the on-chip communication design for embedded heterogeneous multi-core processor. The research in this paper includes two topics:In order to provide an effiencient cooperation mode of on-chip cores, we proposed an architecture model for on-chip communication which called "Main-Synergistic" control model. The basic principle is that the Main core (on-chip processor) assigns tasks to the Synergistic core which then fetches the body of task and executes.With the architecture model above, we designed a low-level connection hierarchy model of the on-chip communication to solve the problem of efficient sharing of on-chip communication path. This model performs both the function of memory hierarchy and the communication paths between on-chip cores, and is called "Unified-Communication" model.After the detail design, the two models are then strictly examined with hardware implementation and cycle-based simulator. The result shows that the performance of our "Main-Synergistic" control model is 23% better than the classic one; and the performance of our "Unified-Communication" model is 1.14 times than the share-cache model and 1.3 times than the share-bus model.In conclusion, our design well overcomes the two problems in the domain of embedded heterogeneous multi-core architectures.