Research Of High-performance, Low-power Multi-core Processors

Since the specific requirements of performance, power, design period and flexibility in the field of communication, multimedia and other applications, neither ASIC-based nor uniprocessor-based SoC can be a good solution for electronic products. Multi-core processor has become the most promising SoC solution for these applications due to its high performance and flexibility. As the hot topic of academic and industrial research, there have been some outstanding multi-core processors. So far, however, none of these designs can be considered as the best multi-core processor due to the complexity and diversification of applications. Thus we are still on the way to find the "best multi-core processor" and there are a lot of problem deserving of study and research.This thesis presents a high-performance and low-power multi-core processor for communication and multi-media applications. On the basis of analyzing the existent outstanding multi-core processors, this thesis pursues innovation of computing, communication and storage design of multi-core processor. The major work of this thesis includes:(1). SIMD-RISC Processor DesignOn the basis of analyzing the MIPS 4KE processor, this thesis presents a SIMD-RISC processor which implements partial MIPS32 ISA and SIMD extension. The SIMD architecture can effectively utilize the data-level parallelism to achieve high performance and high energy efficiency.(2). Configurable RegfileThe proposed SIMD-RISC processor adopts a novel configurable Regfile instead of traditional MlPS-like Regfile. The new Regfile extends its register sum without modifying the instruction width and encoding style. The more available registers eliminate data swap with memory to some extent, which can improve computing efficiency and decrease power dissipation caused by memory access.(3). Cluster-based Network on ChipThis thesis proposes a novel cluster-based NoC for multi-core processor. In the system-leveL the cluster-based processor array is symmetric and flexible. Meanwhile the cluster itself can provide configurable shared memory and effective synchronization mechanism.(4). Hybrid Communication MechanismThe multi-core processor proposed by this thesis provides hybrid communication mechanism:message-passing and shared-memory. The packet-based message-passing is a global and flexible communication mechanism, whereas the shared-memory mechanism aims at inner-cluster communication and can alleviate the network payload by sacrificing shared-memory access bandwidth.(5). VLSI Implementation in TSMC65nm ProcessAfter finishing the RTL design and verification of multi-core processor, the thesis work also includes multi-core VLSI implementation in TSMC65nm process. The chip integrates 16 SIMD-RISC processors, and the chip size is 2935.6*3100um with 124 chip pads. According to IC compiler timing report, the proposed multi-core processor' highest clock frequency can achieve 600MHz at the typical corner. The power dissipation of each processor node in multi-core array is estimated at 80mw.