Design Of A Many-core Processor And Research On Inter-core Communication Issues For Multi-channel Low-bit-rate Vocoders

In military and security fields,low-bit-rate digital speech codec as known as vocoder is widely used,since wireless channel bandwidth is limited by a series of factors including environmental noise,frequency reuse and encrypted communication.As the bit rate of speech is reduced to 300?600 bps,the performance requirement for real-time processing of vocoder algorithms reaches many hundreds of MIPS(Million Instruction Per Second)because of the increased computing complexity.While memory size required by the algorithms also exceeds200 kB due to the increase of codebook data for speech quantification.Both make it more and more difficult to perform low-bit-rate speech encoding and decoding on embedded processors with real-time efficiency.Moreover,in some practical scenarios such as battle command communication and multi-person voice conference,multiple channels of speeches need to be processed simultaneously.The multiplied requirements for performance and memory bring more challenges to the design of processors.By customizing and optimizing instruction set and pipeline architecture,ASIP(Application Specific Instruction Processor)can achieve higher efficiency for specific applications than GPP(General Purpose Processor)and general DSP(Digital Signal Processor),while it also has programmability and configurability which ASIC(Application Specific Integrated Circuit)lacks.Besides,according to the requirement for parallel execution of applications,processors based on heterogeneous many-core architecture can achieve high performance and power efficiency.Therefore,in this dissertation we adopt the design methodology of ASIP to perform research and implementation of a heterogeneous many-core processor for multi-channel low-bit-rate MELPe(Enhanced Mixed Excitation Linear Prediction)vocoder applications.In this dissertation,we first propose a heterogeneous multi-core collaboration solution by locating the performance bottlenecks of the vocoder application.Both performance speedup and power efficiency of heterogeneous many-core processor are modeled and researched.We propose a heterogeneous many-core ASIP for low-bit-rate vocoder applications,which integrates big/little heterogeneous processing cores and a shared-memory core in a 2D mesh NoC.Aiming at the performance bottlenecks of the applications,we design a dedicated ISE(Instruction Set Extension)for processing cores to finish fixed-point number computing and post processing within single instruction.And we adopt a�stage skipping�technique to improve the execution efficiency of extended instructions.Besides,we propose an accelerating technique for nested loops,which reduces the time of processing cores performing loop operations by automatic counting and jumping of loop bodies.Then,inter-core communication issues for NoC manycore processors are researched in this dissertation.Finally,we finish the chip implementation of the heterogeneous many-core ASIP based on SMIC 40 nm process,and realize porting and optimization of the applications.We achieve real-time processing of single-and multi-channel low-bit-rate vocoder applications on the heterogeneous many-core ASIP at a low working frequency.We research the two critical issues of inter-core communications for NoC many-core processors,including multi-core synchronization control and inter-core data transmission,and achieve technique innovations as follows.In the aspect of multi-core synchronization control,aiming at the communication congestion incurred by centralized lock synchronization solutions,we propose a distributed queue lock synchronization technique.Applying distributed polling on synchronization control units of different processing cores within a lock fetching queue,we realize the fetching and releasing of queue locks.A FIFO is adopted in the synchronization control unit to store synchronization requests,which reduces inter-core communication traffic by local polling.The proposed lock synchronization technique can still achieve low latency for synchronization when the number of processing cores increasesAiming at the lack of support for concurrent barriers and the low scalability of previous barrier synchronization solutions,we propose a master-slave barrier synchronization technique based on a NoC adopting a hybrid switching method of PS(Packet Switching)and CS(Circuit Switching).When barrier synchronization requests are transmitted in the PS sub-network,dedicated channels are dynamically built in the CS sub-network to reduce transmission latency.Inter-core communication traffic is effectively reduced by merging synchronization requests in CS crossbars dynamically.Compared to previous solutions,the proposed technique achieves lower synchronization latency,and supports concurrent barriers with high efficiency.In the aspect of inter-core data transmission,aiming at the loss of transmission efficiency incurred by the long setup time of dedicated channels in CS NoC,we propose a low-latency inter-core DMA transmission technique also based on the hybrid PS-CS NoC.When data are transmitted in the PS sub-network,dedicated channels are partially built in the CS sub-network by configuring bidirectional ports of crossbars.According to the subsequent communication requests transmitted in the NoC,dedicated channels can be lengthened dynamically,which reduces data transmission latency further.For concurrent DMA transmissions,applying the proposed technique can significantly improve the efficiency of inter-core data transmission.In conclusion,we design a heterogeneous many-core ASIP for multi-channel low-bit-rate vocoder applications,and research critical issues of inter-core communication for NoC manycore processors.This dissertation provides both theoretical foundation and reference design for the implementation of ASIP with high power efficiency for specific applications.