System-Level Moduling And Evaluating For Multi-core Processor Based On OVP

With the increasing complexity of embedded applications such as multi-media and communication, hardwares with higer performance are in demand. Programmable multi-core processors are drawing much attention due to their higher performance compared with single-core processors. On the other hand, due to the large difficulty of hardware and sofeware development for multi-core processors, it is very important to explore the architecture of multi-core and develop multi-core software using its system-level model. In this way, we can find the optimal architecture and reduce design schedules. In this paper, we propose a novel modeling method for multi-core processors and construct a 64-core multicore virtual platform using this method. The main work and innovation of this thesis are as follows:1. Proposed a novel method for multi-core processor modelingIn this paper we present a fast multi-core virtual platform which employs a high-speed MIPS32LE single-core processor model provided by OVP. Futhermore, we modify the OVP processor model by adding some special instructions. Full custom NoC models wrapped by TLM-2.0 interface are created by SystemC. All the components can be connected by the TLM-2.0 interface and then construct the whole multi-core virtual platform. OVP tool OVPsim can be used to run and simulate the virtual platform with a extremely high speed; Abstract data type represents transmission of multiple clock cycles using TLM2.0 loosely-timed model, which will further accelerate the simulation speed.2. Hardware accelerator modelingIn this paper, we model accelerator of multi-core system using OVP Semihosting mechanism. Accelerator model will be activated when OVPsim meets the corresponding function name. The simulator will then appear to execute one instruction at the intercepted function address. However, this single instruction will perform the entire behavior specified by the interception library for that address.3. NoC Modeling and EvaluationIn this paper, full custom NoC model is constructed. The three compnents of NoC, the network interfaces, the physical link and router, are modeled by SystemC and TLM2.0 interface. This proposed multicore virtual platform integrates third-party tools ORION2.0, which can be used to evaluate NoC area and power consumption. In addition, FIFO depth can be explored by tracing its signal.4. Multi-core Software EvaluationIn this paper, we proposed a method to evaluate software application performances using the multi-core virtual platform. The simulator OVPsim can caculate executed instruction number of each core. As a result, we can use instruction number to estimate execution time of each core by assuming that one executed instruction costs one clock cycle. We can explore the partition strategy and mapping scheme of multi-core software applications. In this paper, LTE downlink receiving channel carrier frequency synchronization application is evaluated using the multi-core virtual platform.