Study On Low-Power Technologies Of High-Performance Embedded Processors

Entering the 21st Century,with the development of integrated circuit technologies,the development of microprocessor chip has encountered many opportunities and chanllenges.Power consumption is one of the main constraints of processor design.Especially for embedded processors,power consumption is much more important because of the embedded system's size,the battery capacity and the portability of mobile devices.Along with the social development and advancement of science and technology,applications such as multimedia area,entertainment area,web browering and others on the desktop system are gradually popular in embedded systems.All these applications require very high performance embedded processors. So researchers need to design high-performance embedded processors under low power envelope.The work in this thesis carried deeply research on the power issues of high-performance embedded processors and the work mainly includes three aspects: processor power consumption estimation technique,structural level power optimization of embedded processors and the power efficiency of heterogeneous processors.The following are the main contributions of this thesis:1.Implementation of a fast and accurate estimation method of processor power consumption based on FPGA.This method utilizes the RTL code of microprocessor,retrieves each modules' power consumption data by using standard cell libraries and EDA tools.Meanwhile,the module access information is acquired from FPGA platform.Based on the above data,the power consumption of the processor can be calculated.The precision of this method has been verified with high accuration by comparing with the results of EDA power analysis tools.A large number of programs' running power are analyzed by using this method on the FPGA platform afterwards.This method can also dynamicly record the varity of power comsumption and it is much faster than structural level power simulator and gate-level power analyzer. With the property of high accuracy,this method provides a fast,efficient and accurate power estimation platform for low-power processor design.2.Proposed embedded processor design based on Delay-Writeback technique. This thesis implemented register file delay-writeback in Godson GS232 processor and the power consumption of register file is much reduced.To lower the power consumption of the processor further,fetch-throttling is applied and the ICache's power is also reduced.The proposed power estimation method is used to evaluate the processor's power.3.Proposed heterogeneous processor's power consumption analysis model.The power consumption is lower if a program runs on a small processor core, rather than on a large core.That's due to the following two reasons:1) the proportion of leakage power to the total power is becoming higher along with the technology's advancement,and processor will waste energy when it's in idle state;2) Small CPU core has much higher performance/power ratio than large processor core.So by letting some programs which require low performance run on the small core can save a lot of energy.This thesis simulates program's behavior by using poisson process and adopting the actual power consumption record of programs.The results of the simulation experiments proved that heterogeneous processors are energy-saving.Aiming to design high-performance embedded processors,this thesis achieves some significant innovations with excellent practicability by focusing on low-power research and parts of the innovations can be applied directly on the design of GS232 processor,and also provides references for the design of future heterogeneous high-performance embedded processors.