Design And Implementation Of A Low Power Processor Based On 28nm Process

With the development of semiconductor technology,the complexity and running speed of the circuit increase rapidly,resulting in a significant increase in power density and power consumption.Processor power has become a measure of speed and area.In this paper,a RISC-V processor based on low power design work,the main work is as follows:First,the power consumption in IC is analyzed,and several low-power methods and matters needing attention in use are introduced,then three power analysis strategies are introduced.Secondly,through the types of front-end simulation control instructions,this paper puts the processor in three power consumption modes,which are to achieve High power mode,Low power mode,and Middle power mode in between.These three types of instructions are used to distinguish the number of load,store,and division instructions executed by the hardware.The purpose is to make the power analysis as close to the actual application value as possible.Finally,the clock gating,multi-threshold voltage,and multi-voltage based on UPF are designed for the single-core design of the processor.Three power analysis strategies are used to analyze and summarize the power consumption of the low-power design.At the same time,in addition to the clock gating,multi-threshold voltages and multi-voltages,the dual-core design of the processor is also used to power gating supply strategy,and the power consumption analysis and comparison after the low power consumption strategy are performed.It is concluded that the control timing is unchanged.When using the three methods for a single-core processor,the total power consumption in High power mode is reduced by about 39.5%,the total power consumption in Middle power mode is reduced by about 37.8%,and the total power consumption in Low power mode is reduced by about 36.9%,while the area is reduced by about 12%.When using these three methods to control the timing of dual-core processors,the total power consumption is reduced by approximately 41.8% in High power mode,approximately 37% in Middle power mode,and approximately 38.9% in Low power mode.At the same time,the area is reduced by about 17%.The overall result is satisfactory.At the same time,logic equivalence checking is carried out to reduce the power consumption under the premise of ensuring the correct function.