| Embedded processors, deeply integrated and utilized for a multitude of SOC sub-systems, have already established themselves as the unquestionable leader in terms of volumes, electronic market share, and revenues, greatly surpassing their close relatives, the general-purpose processors. The general-purpose nature of the microarchitecture of such embedded processors imposes the leading technical challenges associated with them, namely, excessive power consumption and lower performance compared to a custom designed solution.; The objective of this thesis is the definition of a new embedded processor architecture capable of incorporating and utilizing application knowledge within the processor micro-architecture so as to achieve significant power and performance improvements. The basic approach is to identify global and local application properties during compile/link time and/or through profiling and exploit them dynamically during program execution by the processor. The application properties are utilized by a microarchitecturally reprogrammable hardware, thus maintaining the flexibility and the consequent low design and verification cost as no new silicon spins or VLSI design reiterations are required in the face of new application targets or software modifications.; The customization policy introduces a reprogrammable hardware support, to be used as a customization vehicle for various micro-architectural features, such as data/instruction caches, branch resolution logic, on/of chip memory communication, etc. The reprogrammable logic includes tables of programmable registers, a reconfigurable data path and memory cells. This logic aims to enhance the microprocessor architecture with application-specific properties. The proposed customization logic is reprogrammable in the sense of loading a set of registers or tables with specific values for controlling simple data paths or for defining certain special events for the particular application. (Abstract shortened by UMI.)... |
