Power Dissipation Estimation And Low Power Design For Integrated-Circuits

As manufacture technology scaling down, power dissipation has become a critical issue of VLSI circuit design, in which dynamic power dissipation estimation and optimization are traditionally included. When deep into sub-micro process, some new problems have been detected, such as exponential increase of leakage power that leads to a series of significant hot topics. This is the background of this paper. Some subjects are discussed: leakage power evaluation, leakage power optimization and some other related problems.1. Power estimation and optimization experimental platform for Very Large-Scale Integrated (VLSI) Circuits. Based on many other circuit formats, a new kind of logic-level circuit representation, called unified middle-level circuit format (UMCF), is defined in this paper , in which some special operations on circuit related with power estimation and low power design. UMCF can not only interchange circuits of different formats, but also convert circuits to HSPICE acceptable files, which can be used for transistor level power estimation. UMCF can verify our own simulation results on popular accurate power estimator including transition-based dynamic power estimation, hazard/power-up power estimation, high-complexity leakage power estimation etc. High-dependable and high-efficient experiment environment is the base of this whole dissertation.2. Dynamic power estimation and optimization. Power sensitivity is defined and some related mathematical models are deduced, which bring on a set of theoretic power sensitivity analysis methods for combinational circuits. Experimental results verify that the method can be used for dynamic power and leakage power. Also the hazard resonance phenomenon of benchmark circuits is detected, which can be used to accelerate the power estimation with very good results. At the same time, a transient dynamic power estimation method aiming at power-up circuits is proposed, the appropriative power model and simulation result are detailed in this paper. Input vector control is very popular method to deal with dynamic power, part of the unsolved problem of which is also discussed. The research of dynamic power will contribute to the deep-in understand of the power behavior under low process. This part is the basis of low power technology of deep-sub micro technology.3. Leakage power estimation and optimization. With the popular sources and models of static power fully discussed at first, the stack effect of transistor-level and logic-level CMOS circuits are analyzed in detail according to the broadly adopted UC Berkeley BSIM model. A low-complexity logic-level leakage power model is proposed, according to which a fast table-lookup based static power simulator is...