Low-power Research On High Performance General-purpose Processor Core Design

High performance general-purpose processor design is the key technology of current VLSI design. As VLSI technology developing rapidly in complexity and density, power consumption of chips has become a major concern in the state of art high-performance CPU design. This problem has been even a main challenge to Moore's law.This thesis focuses on low power research on the high performance general-purpose processor design, which is based on Godson-2 processor core. Many creative methods are raised in this paper. The following is the main contributions of this thesis:1. Speed-up techniques for gate-level power estimation are proposed. An efficient power estimation flow is presented firstly to reduce the power simulation time. In addition, a novel heuristic approach which we called"improved simulated annealing algorithm"is proposed for bounding maximum and minimum leakage power.2. A design method for low power clock network is proposed. According to elaborate analysis of clock logic in general purpose processor, we apply multi-bit clock gated flip-flops design to reduce the power of registers and clock trees concurrently, so the power of the clock network in processors can be drastically reduced.3. A low power issue queue architecture is proposed. According to Godson-2 issue queue analysis, we modify the conventional issue queue's structure for low power without loss of performance, thus reduced area and power.4. Low power techniques for accessing register-file are proposed. To achieve this, an architectural power model for multi-port register-file is presented firstly. Based this model, several practical optimization techniques are applied to reduce the power of register-file. The experimental results show that these techniques can reduce about half power of register-files in Godson-2.5. Low power techniques for high performance functional units design are proposed. A design method which combines"operand isolation"with"input vector control"techniques is proposed, and this method can reduce dynamic power and leakage power concurrently in functional units. Especially, the low power designs for floating-point adder and multiplier are also proposed and discussed detailedly and...