| Microprocessor clock frequencies have increased to meet the rising performance demands of applications. This increase in clock frequencies has led to a corresponding increase in the power consumption of high performance microprocessors. Increasing power consumption poses challenges in processor cooling and obtaining long battery life in mobile systems. Because of these problems it is now important to consider power-efficiency at all levels of microprocessor design, including the level of the processor architecture.; The optimizations we discuss are architecture-level optimizations which address power challenges in microprocessors while maintaining a high level of performance. The specific contributions include: architecture-level power optimizations for simultaneous multithreading processors, optimizations which use dynamic critical path information to reduce the necessity of high power structures for performance, a study into the limits of architecture-level power optimizations on modern architectures, and a study of the effect of compiler optimizations on processor power consumption. |
