Research On Vector Multipliers Oriented To Pre-Carried Optimization

Due to the rapid development of artificial intelligence in recent years,the efficiency of hardware resources in performing AI-related operations is low due to its operation-intensive characteristics,and how to make hardware resources meet the needs of AI is a major problem facing hardware.Neural network is the representative of artificial intelligence algorithm,and more than 95% of neural network operations are vector multiplication and addition operations,therefore,how to implement efficient vector multiplication and addition operations is a major research hotspot at present.In the dissertation,a vector multiplier architecture oriented to pre-feed optimization is proposed for the computation of neural networks.From the physical implementation optimization,the high and low bit segmented outputs of the pre-stage digital-to-analog conversion and analog weighting circuits are used to pre-feed the low bit in the corresponding post-stage high bit analog-to-digital conversion to obtain the quantized digital output of the final vector multiplier.Based on the above architecture,a circuit implementation of vector multiplier optimized for pre-feeding is carried out,which consists of two main circuits: the multiplication and addition calculation circuit and the SAR ADC pre-feeding circuit.The multiply-add computation circuit splits the input symmetrically,completes the weighted calculation of the two input parts and weights,reduces the area of the multiply-add computation circuit by weighting the weights in a hierarchical manner,and transmits the calculation results to the SAR ADC in the form of analog voltage;the SAR ADC pre-feed circuit combines the symmetrical splitting of the input and pre-feeds the results of the first part of the calculation,and the pre-feed output is used to supplement the low-bit output by the second part of the calculation.The second part of the computed output is used to supplement the low-bit result.The proposed vector multiplier optimized for pre-feeding is functionally verified and performance tested,and the experimental results show that the proposed vector multiplier achieves improved throughput,energy efficiency,and computational density.