Design Of High-speed ECC Algorithm Coprocessor

According to the requirement of the high data throughput of authorization service, ECC public-key cryptosystems based high-speed ECC chip is an effective solution. In which, the throughout of ECC chip plays an important role in ECC public-key cryptosystems. To improve the throughout of ECC chip, the main research task of the thesis is a high-speed hardware implementation of ECC algorithm.This thesis presents ECC algorithm which implements the operation of general Elliptic curve defined over the prime field . In algorithm level, hardware implementation of ECC algorithm is based on the dual modular multiplier architecture with pipeline and systolic. Modular multiplication algorithm is the improved Montgomery algorithm. The algorithm breaks up the bottleneck of Montgomery algorithm formed by"no final subtractions"and"quotient determination". Point multiplication algorithm is"from left to right"algorithm, in which, recoding is Non Adjacent Form(NAF). The point coordinate representation of point over is Modified Jacobian Maxed coordinates. For improving the hardware efficiency of the pipeline and systolic dual modular multiplier, this thesis rearranges the operation sequence, then makes point addition need 7 modular multiplication cycles and point doubling need 4 modular multiplication cycles. In high-speed ECC, the modular multiplication cycle of point multiplication algorithm are 6.3L(L approximately equals the modular bit-length).The high-speed hardware implementation of ECC algorithm applies to the ECC ASIC high chip.With the frequency of chip 100 MHz. and 192-bit prime modulus, it performs 6000 times point multiplication operation per second. For 256-bit prime modulus, it performs 3000 times point multiplication operation per second.