Research And Design Of Floating Gate Based Vector-Matrix Multiplier For Neural Network

With the development of deep learning in recent years,neural networks have be-come more and more widely used in many fields such as image recognition,speech recognition,and natural language processing.However,as the network architecture becomes more and more complex,the amount of computation required by neural net-works has increased dramatically.At the same time,the large amount of input and output data required makes data transmission a major bottleneck that limits speed.In addition,computing and data transmission bring tremendous power consumption,mak-ing neural network applications difficult to deploy on edge devices.Research on the new computation architecture can solve the data transmission bottleneck caused by the separation of memory and computation of the von Neumann architecture through in-memory processing.Aiming at the application requirements of neural networks,this thesis designed a vector-matrix multiplier(VMM)with processing in memory(PIM)architecture based on floating-gate cells of NOR flash.The main research work and innovation of this thesis are as follows:1.The principle of the analog multiplication on floating gate cells was researched.The floating gate cells worked in the linear region when performing analog multiplica-tion.Two floating gate cells were used to store one weight differentially.Compared with the single floating gate cell,the computation linearity was improved.The distribu-tion of weights' temperature coefficients was reduced,and zero temperature coefficients can be achieved through compensation.2.A analog vector-matrix multiplication circuit was designed based on floating gate cells,including the design of flash memory array,current subtraction circuit,cur-rent buffer circuit,and temperature compensation load circuit.The flash memory array realized data storage and multiply-accumulate operations.The current subtraction cir-cuit and buffer circuit implemented current subtraction and impedance transformation to accurately calculate the multiply-accumulate results.The load circuit compensated the temperature characteristics of the floating gate pair,so that the analog multiplication results had good temperature characteristics.3.Auxiliary circuits for the interface between digital and analog were designed,including behavior-level modeling of digital-to-analog converters(DAC)and analog-to-digital converters(ADC),and analog vector-matrix multiplication circuits were con-nected to external digital circuits.4.The MNIST neural network was used for circuit verification,and a full ana-log circuit implementation scheme was proposed.System was based on the proposed vector-matrix multiplication circuit,and the circuit scheme expansions of the convo-lutional layer,pooling layer,and fully connected layer were proposed.For the small application,the system could complete the recognition on-chip,and directly output the recognition results,eliminating the need for ADC and external data scheduling,reduc-ing the power consumption.The circuit design was based on the XMC 65nm floating gate process,with a power supply voltage of 1.8V,Simulation was performed using Cadence Spectre,and behavioral modeling was described using Verilog-A.The accuracy of the system was 4 bits(inputs were 4-bit unsigned,weights were 5-bit signed,outputs were 4-bit un-signed with ReLU activation function).The size of flash array for vector-matrix analog multiplication was 32×32.The maximum clock frequency was 26MHz,and power con-sumption was 0.7?1.8mA.The layout area used for analog computation was 0.028mm2.The temperature coefficient of the stored weights was less than 0.06%/? from-40? to 130?.The throughput was 1.66GOPS,and the power efficiency was 0.47?1.09TOPS/W.The MNIST neural network had 1718 weights.The recognition rate was 4.15×103fps,and the recognition accuracy rate was 97.67%.