| As Moore’s Law and Desnard’s Law of scaling slow down and stall,the cost performance gains from chip manufacturing upgrades become less and less cost-effective.In this context,chiplet heterogeneous integration technology has been widely concerned as a possible key technology to solve the above problems.Due to the special stacking structure,the internal of chiplet has opacity,poor observable and controllability,and the test pins of chiplet cannot be fully encapsulated after binding.As a result,the number of available test ports decreases and the difficulty of test access increases.The development of chiplet faces challenges in testability design.Aiming at the above problems,this thesis brings forward a Flexible Configurable Modules(FCM)suitable for multiple test scenarios.FCM can be used to establish the direct interconnection between the main interface,the secondary interface and the core functional logic of the chip to satisfy the data exchange between the complex heterogeneous integrated chiplet and the transformation of the test mode,so as to improve the flexibility and controllability of the test.Then,a test access control circuit for the post-binding chiplet is designed based on FCM,which is compatible with JTAG network and contains a chiplet test controller,a test control circuit based on FCM and a test control signal configuration module.The test access control circuit of chiplet based on FCM can serial control the TAP controller and scan input/output ports of the small chip in chiplet respectively,realize the independent test of the small chip in chiplet,and solve the test access problem of chiplet.The chiplet test access control circuit based on FCM is mainly applied to chiplet memory test and scan test.For the chiplet memory test,the chiplet memory test control circuit based on FCM makes full use of the vertical transmission characteristics of FCM.This circuit can connect the JTAG port of the chiplet in the chiplet serial and realize the control of the MBIST circuit in the chiplet,and complete an independent test of the post-binding chiplet memory.For the chiplet scan test,the chiplet scan test control circuit based on FCM utilizes the horizontal bidirectional transmission characteristic of FCM.By controlling the scan input/output port and data transmission line of the small chip in chiplet,the on-off state and data transmission direction of the scan test path can be controlled.Thus,the scanning test of small chip inside chiplet can be completed independently.In this thesis,an experimental circuit consisting of three microchips and an active interposer is constructed.The simulation results show that the proposed chiplet testability circuit based on FCM can reuse the original testability structure,meet the plug-and-play strategy,and solve the testing problem of the post-binding chiplet.Compared with the circuit designed based on TAP controller,the proposed chiplet controller area is reduced by39.51%,and the total test control circuit area of chiplet is 22255.02μm~2,accounting for only 3.12%of the total circuit area.The post-binding test of chiplet can be completed by using only 5 JTAG ports and 6 scan test ports,which reduces the cost of the test port and verifies the practicability and correctness of the test control circuit of chiplet based on FCM. |
