Design Of 10-Gb/s CMOS Inductorless Low Power Transimpedance Amplifier Chip

With the rapid development of the digital economy and the continuous promotion of 10G passive optical network（PON）,the global demand for optical communication chips is continuously increasing.The transimpedance amplifier（TIA）,as the core optical communication chip of the optical receiver,directly affects the performance of the entire optical fiber system.However,due to the low domestication rate of high-end TIA chips,there is a bottleneck problem in this field,which restricts the development of China’s optical communication industry.Therefore,this paper focuses on the research of TIA in the optical network unit side of10G PON system,and designs a low-power,inductorless 10-Gb/s TIA based on 65nm CMOS technology for Gigabit optical network applications.One of the challenges in designing CMOS transimpedance amplifiers is the large parasitic capacitance introduced by avalanche photodiodes（APD）at the optoelectronic interface,which severely limits the bandwidth and reduces the sensitivity of the chip.Another important challenge is that the unit current transconductance of CMOS technology is smaller than that of Si Ge technology.Therefore,to achieve performance comparable to Si Ge TIA,the power consumption of CMOS TIA will sharply increase.To overcome these challenges,this paper proposes the following innovative solutions.To address the bottleneck problem at the optoelectronic interface,this paper proposes a new TIA architecture by integrating equalization and current injection techniques.The bandwidth of the TIA input stage is set relatively low,and then the equalization technology is used for high frequency compensation,which not only extends the bandwidth to the required standard,but also increases the feedback resistor,which significantly improves the noise performance of the transimpedance amplifier.The use of current injection techniques effectively alleviates the trade-off between transimpedance gain and bandwidth of the TIA.To achieve inductorless bandwidth extension,this paper proposes a Gate-Drain Cancellation（GDC）technique,which increases the main channel bandwidth of the TIA by 37.5%.The above techniques make the designed TIA capable of driving low-cost narrow-band APDs for high-speed applications in Gigabit optical fiber networks.To address the design challenge of power consumption,this paper proposes a novel tail current reuse circuit that reuses the tail current of the output buffer stage and injects it into the input stage of the transimpedance amplifier.This provides the TIA with a larger input transistor transconductance,and solves the coupling problem that may arise from tail current reuse circuit at the circuit design level.The circuit enables the chip to achieve larger bandwidth and lower noise,while saving 20%of power consumption,providing a new approach to break through the power consumption limit of CMOS TIA.This paper has completed the circuit,layout design,and chip testing of the transimpedance amplifier,and achieved excellent performance indicators.The measured overall chip area is 0.56mm²,with a power consumption of about 86m W at a supply voltage of 3.3V.The transimpedance gain of the chip is 66 d BΩ,the bandwidth is 6.8GHz,and the average input-referred noise current is 11.9p A/√Hz.At a bit error rate of 1e^-12,the average sensitivity of multiple chips is-22.4d Bm,and the figure of merit（FOM）is 6.63.These results demonstrate that the innovative solution proposed in this paper has achieved a high-performance,low-cost transimpedance amplifier,providing a new approach and direction for achieving high-speed,efficient,and low-cost transmission in the Gigabit optical fiber field.