Research And Design Of Row-Column Driver System For Floating-Gate CIM Devices

Currently the integrated circuit technology is approaching the limit of Moore’s Law.The compute-in-memory(CIM)technology,as a new computing architecture that integrates storage units and computing units,can greatly reduce the data exchange time and the energy consumption of data access by transferring the calculation process from the central processing unit to the memory.Using the floating-gate(FG)device as the storage and calculation unit has the advantages of high storage accuracy and low power consumption.However,high voltages ranging from-10 V to 10 V are required in the working mode and working state,which is determined by the characteristics of FG device.In order to realize the storage and calculation functions of the CIM array of FG devices,the peripheral drive system must be able to realize the generation,switching and transmission of multiple high voltages for word/bit/source lines.In this thesis,the research and design of row-column driver system for FG CIM devices are carried out.Through the driver system,various high voltages are generated and controlled to realize high-speed switching of working modes and working states such as programming,reading,and erasing of the CIM array,which can promote the development CIM chips towards higher integration.The main research content of this thesis is summarized as follows.(1)Starting from the working principle analysis of FG CIM device,the mechanisms of the three working modes of programming,reading and erasing of the CIM array are explained by comparing the two flash memory array architectures of NOR Flash and NAND Flash.Aiming at the operation characteristics of multi-voltage and multi-mode switching of CIM arrays of FG devices,and considering the requirements of CIM chips for the driver system,a row-column driver system composed of digital control logic circuit,mode conversion circuit,word/bit/source line driver circuits and on-chip charge pump are proposed for the CIM array.(2)Aiming at different requirements of word line readout and programming of CIM arrays,a word line driver system architecture with separated read and write is proposed.Since the bit line and source line voltage requirements are similar and the area ratio is too large,a bit line/source line merged driver circuit is proposed by combining with the switch control.Through the digital control logic module,the system control of the large-scale drive circuit is realized,and the number of IOs is reduced.Simulation results show that the output voltage of a single word line programming driver circuit can range from-10 V to 10 V,and the transmission delay in the fixed mode is 7.98 ns.The output voltage of a single word line readout driver circuit can range from 5 V to 0 V with a delay of only 2.59 ns,and the transmission delay of a single bit source line is 5.48 ns.The word line driver circuit can control and transmit two voltages with a voltage difference of 20 V,and the bit source line drive circuit can switch modes and states under the control of the switch tube.(3)A four-phase clock cross-coupled negative voltage charge pump is designed for the situation since the word line of the CIM array needs negative high voltage in the erasing mode.By comparing various voltage stabilizing circuits,a SKIP mode voltage stabilizing circuit suitable for the negative high voltage of CIM array is proposed.In the design of the voltage stabilizing circuit architecture,the charge pump is designed to enter the holding state when it reaches the target voltage by making full use of the feature that the load of CIM array is equivalent to a capacitor for the driving circuit.As a result,the static power consumption of the overall circuit can be reduced.(4)By analyzing factors such as matching errors,a full-customized physical design of driver system for the CIM array of FG devices is completed.The driver system designed in this work can be used in a reasonable arrangement for a CIM array with a size of 3000 μm × 1500μm.Simulation results show that the readout state switching time of the high-voltage control circuit is 10.56 ns.The charge pump has a build-up time of 7.85 μs,the voltage ripple is 24.7m V,and the power consumption of the overall driving circuit is about 28.6 m W.