FPGA Implementation Of Video Scaling System Based On Double Cubic Interpolation Algorithm

With the continuous improvement of computer computing power,all kinds of video image processing technology has also been rapid development.Among them,video image scaling is a very important video image technology,image scaling algorithm directly affects the quality of image display.The computing complexity of high quality video image scaling algorithm is generally high,which will lead to high hardware complexity and low efficiency when video scaling system is implemented.How to improve the quality of video image display and reduce the consumption of hardware resources is a key problem in video scaling system implementation.In order to balance the image quality and hardware complexity of video scaling system,this paper studies the FPGA implementation method of video scaling system based on bicubic linear interpolation algorithm.The main research contents are as follows:(1)The advantages and disadvantages of image scaling interpolation algorithms such as nearest neighbor interpolation,bilinear interpolation,and bicubic interpolation are introduced and analyzed.Subjective and objective evaluation criteria were used to evaluate different interpolation algorithms.The evaluation results show that the bicubic interpolation algorithm has higher display quality than the nearest neighbor interpolation and bilinear interpolation.Therefore,this paper chooses the double cubic interpolation algorithm to implement the video scaling system.(2)Aiming at the problems of high computational complexity,high resource consumption and low efficiency of bicubic interpolation algorithm,a circuit optimization method of bicubic interpolation algorithm based on shared common items is proposed in this paper.Firstly,the calculation formula of interpolation coefficient in bicubic interpolation is constructed.Secondly,the method of eliminating common items is used to extract the common items in the calculation formula of interpolation coefficients.Finally,a bicubic interpolation circuit is constructed according to the optimized formula.The theoretical analysis results show that the number of floating-point multipliers can be reduced from 36 to 20 by the method of common term merging operation,which reduces the consumption of hardware resources.Furthermore,Vivado development tool of Xilinx company of AMD was used to synthesize the bicubic interpolation arithmetic circuit.The comprehensive results show that the proposed circuit optimization method based on shared common terms can reduce the consumption of hardware circuit resources better than the existing optimization methods without affecting the image scaling quality.(3)Based on the optimized bicubic interpolation arithmetic circuit,the FPGA verification platform of video scaling system is further built.The video scaling system is composed of OV5640 sensor module,dynamic random storage data interaction module,scaling algorithm module,display module,and so on.Each module is described by hardware description language,and then AMD-Xilinx Vivado development tool is used for circuit synthesis,layout and wiring.Finally,the video scaling system designed in this paper is simulated and verified on AMD-Xilinx A7 series FPGA platform.The video scaling system designed in this paper has a maximum operating frequency of 200 MHz and can process video signals with resolution from 1280×720p to 1920×1080p in real time.