Design Of Ultra-High Speed Array Camera Electronic Control System Based On FPGA

Ultra-high-speed cameras are widely used in industrial production,scientific research,aerospace exploration and other fields.At present,the image resolution generated by high frame rate cameras is low,which cannot meet the requirements of engineering applications.Therefore,this paper adopts the form of multi-camera array to improve the imaging resolution.In addition,in the high frame rate and high resolution imaging mode of the array camera,the processing and transmission bandwidth required by the system are high,and common image solutions based on platforms such as PC processors and ARM microcontrollers cannot meet the high bandwidth processing requirements.At the same time,due to the asynchronous working characteristics of array cameras,the imaging and data synchronization timing requirements between cameras are strict.This puts forward higher requirements on the parallel processing capability of the system.In recent years,FPGA has become a mainstream research platform in the field of image processing by virtue of its high reconfigurability and parallel acceleration capabilities.This paper puts forward the design idea of "multi-interconnection,level-by-level distribution,and complementary advantages".The main contribution is the design of a configurable generalized and high-speed array camera electronic control system.First of all,this paper starts with the principles required by the array camera electronic control system,analyzes various AXI protocols involved in system transmission,and designs a general protocol conversion bridge.Secondly,in view of the problem of insufficient multi-camera transmission bandwidth in traditional processors,this paper analyzes the Aurora high-speed transmission bus and the on-chip integrated PCIe communication framework.Aiming at the problem of insufficient bandwidth,a multi-endpoint synchronous optical fiber communication array and on-chip PCIe communication network for array camera data reporting and parameter configuration are designed,which effectively improves the system data processing bandwidth.Subsequently,through the research of various DMA transfer technologies,a multichannel scatter-gather DMA transfer structure is proposed according to the characteristics of multicore heterogeneous processors.In addition,for the multi-camera synchronization problem,this paper proposes an array camera synchronization mechanism with multi-channel distribution of homologous trigger signals,and implements the multi-camera streaming data synchronization logic based on the optical fiber communication array design.In order to reduce system interference and improve electromagnetic compatibility,this paper analyzes the relevant principles of signal crosstalk and reflection from the perspective of high-speed circuit signal integrity.On this basis,this paper designs the front-end and back-end FPGA hardware platforms with Zynq MPSo C and Virtex-7 as the core,and proposes corresponding interference suppression methods for high-speed circuit design.This paper also analyzes the power consumption of the system,and designs a multi-level power supply network with low noise and anti-interference.Finally,this paper tests the hardware platform,logic control and software functions of the array camera electronic control system.In order to verify the completeness of the system,this paper splits the functions of the electronic control system platform,establishes a variety of test scenarios,and independently verifies each functional unit.In the 3×3 array test mode,the electronic control system can process 1000 frames of images per second,and the effective data bandwidth reaches 4.719 Gbps.The test results are in line with expectations from electrical characteristics,interface performance to overall functional verification.In addition,the system is highly scalable,supports the connection of multi-size camera arrays,and can meet data transmission up to 18.875 Gbps in a 6×6 array structure.