Design Of PCIE Bus Interface And Fiber-optic Communication Module Based On FPGA

With the continuous improvement of the performance of computer, the CPU clockfrequency and the bandwidth of computer peripheral interface increase in an exponentialway, which leds to a corresponding increasement in the data throughput of the processor.PCI and PCI-X bus, represented as the second-generation bus standard, have limitations inbandwidth and scalability, which has been unable to meet the growing demand of thesystem. Then PCI Express bus emerges as the times require. its advanced systemarchitecture, flexible scalability and high bandwidth makes the PCI Express promptlyadapt to the field with high-speed and real-time requirements. It is obvious that PCIExpress bus will be the leader of this field in the next few years.A design of hardware system realising PCI Express bus interface and fiber-opticcommunication module is given in the paper. This design whose physical structure isbased on the PCI Express2.0standard uses a high-performance Virtex-6FPGA as the coreof the system. PCI Express bus in this system can be expanded up to8channels, whichcan support the maximum bandwidth of40Gbps in theory. At the same time, the systemprovides an easily replaced IO interface, which can patch fiber optic module, making itconvenient achieving high-speed data transfer between the host and peripherals.Firstly, The performance of three-generation bus protocols, including the PCI Expressbus standard, is compared in the paper, summing up the advantage of PCI Expresstechnology, and forecasting its developing trends in the future. Then, a detailed analysis ofPCI Express bus are made, including it’s system architecture, hierarchy, transactionmechanisms, as well as the configuration space. In the following, the paper sums up thekey technologiy and knowledge.involved in the research.Then, the paper discusses the FPGA hardware design and logic design in detail. Theformer mainly includes the general scheme design and board-level design of the systemhardware. The latter carries out a detailed analysis of the core module in the logic design,such as PCI Express DMA data-transfer method, fiber-optic communication based onAurora protocol, whose timing diagrams and Verilog codes are also gived. Finally, the paper illustrates the timing simulation and verification of the dedign withModelsim and Chipscope, to ensure that the design is correct and reasonable. And theresults can prove that the program above is feasible.