Research On Column-parallel SAR/SS ADC With Multi-Column Shared Capacitor DAC

As the eyes for electronic devices to perceive nature,CMOS image sensors are developing towards higher resolution and faster acquisition speed in order to display natural images more truly.ADC is the key module of CMOS image sensor.In high speed and high resolution CMOS image sensor,column-parallel ADC has become the mainstream of image quantization circuit.With the decreasing of the single pixel size of CMOS image sensor,higher requirements are put forward for the speed and area of column-parallel ADC under the condition of limited column width.In order to meet the performance requirements of small-size pixel image sensor for columnparallel ADC,a column-parallel SAR/SS ADC structure with multi-column shared DAC capacitor is proposed.Firstly,the SAR/SS two-step ADC circuit structure is built by taking advantage of the fast conversion rate of SAR ADC and the simple structure of SS ADC circuit.The performance of ADC circuit when SAR and SS are implemented with different bits in twostep architecture is analyzed.Considering the requirements of speed and area,a circuit implementation scheme of SAR structure for high 6-bit and SS structure for low 6-bit ADC is determined.Further according to the characteristics of the circuit structure,the high 6-bit SAR ADC and low 6-bit SS ADC use 20MHz and 40MHz respectively to further improve the A/D conversion rate.Secondly,in view of the large area of capacitor DAC in high-bit SAR,which cannot meet the requirement of column width,the technical scheme of multi-column shared capacitor DAC is studied and discussed.Based on the restriction of the width,the conversion speed and the requirement of precision,the circuit structure of eight-column circuits sharing one capacitor DAC array is given.Meanwhile,the dummy capacitor in capacitor DAC is used to store the output voltage after the end of high-bit quantization each column of the shared columns to ensure the correct quantization.The ADC studied in this paper is implemented by UMC110nm CMOS technology.The analog and digital supply voltages are 3.3V and 1.2V,respectively.Cadence platform is used to complete the circuit and layout design and simulation verification.The post-simulation results show that DNL and INL are+0.4LSB/-0.3LSB and+0.3LSB/-0.9LSB,respectively.The 18.92kHz input sinusoidal signal is sampled at the sampling frequency of 192.307kS/s,and the SFDR,THD,SNR,SNDR and ENOB are 85.7dB,-83.4 dB,65.3 dB,63.5dB and 10.72-bit,respectively.The layout area of single column is 5μm×1843μm.