Design And Implementation Of Time Triggered Fiber Network Switch

As a high-speed bus,Fiber Channel has the characteristics of strong anti-interference,safety and reliability,and its avionics environmental protocol cluster has made Fiber Channel mature in avionics networks,and with the upgrading of avionics networks,avionics network puts forward higher requirements for airborne data bus.The determinism,real-time and low latency of time-triggered network is in line with the development trend of airborne network,and time-triggered Fiber Channel has become the top priority of next-generation avionics network research.Based on the theory of time-triggered Ethernet protocol and Fiber Channel protocol,this thesis designs and implements the key node switch of time-triggered Fiber Channel network.In order to effectively improve the switching efficiency,this thesis classifies and schedules services in the network,and adopts the dual-switching structure to ensure the determinism and real-time of time-triggered services.The scheduling of event-triggered services adds the traffic adaptive function based on the i SLIP algorithm,so that the non-uniformity of ET traffic no longer affects the switching efficiency,and the throughput rate of network ET traffic is significantly improved.The main work of this thesis is as follows:1.Introduce the time-triggered AS6802 protocol in detail,explain its key algorithms and synchronization mechanisms,and propose improvement schemes.2.In order to effectively solve the priority blocking problem of ET packets in TTFC network,an implementation method of system-on-chip system based on priority rearrangeable virtual output queues is proposed,and VOQ is built by using the cache structure with address information,which makes queue reconstruction possible and avoids blocking RC packets by unforwarded BE packets in the cache queue.3.Analyze the iSLIP scheduling algorithm,and propose a traffic adaptive scheduling scheme for the problem of reducing scheduling efficiency under non-uniform traffic: set different priorities for exchange frame requests,and dynamically adjust the priority of requests according to VOQ cache queue length,frame waiting time and current request frame length,so that ports with large traffic can establish more data paths to complete data exchange,and verify the performance improvement of the algorithm through simulation modeling.4.Based on FPGA chip,the design scheme of TTFC switch is proposed,and simulation and experimental verification are carried out.According to the different functions,the TTFC switch is divided into clock synchronization,data cache,input scheduling,switching structure,output scheduling,and data listening modules,and the above modules are designed and interface defined in detail.Through Modelsim software,each module is simulated,for the clock synchronization module,the permanence algorithm and the compression algorithm process are simulated,and the compression algorithm opened by four error nodes is simulated under the premise of double fault-tolerant system,so as to fully verify the stability of the clock synchronization function;For the input scheduling module,randomly generate simulation data input to the VOQ cache,observe the dynamic adjustment of the request priority process of the input scheduling module,input the request to the output scheduling module,and observe the authorization of the output scheduling module.After the simulation is verified,a 12-port TTFC switch network is built,the switch signal is captured,and the synchronization accuracy is only about 100 ns.Configure different packet data to verify the unicast and multicast functions of the TTFC switch,and complete the board-level verification of the designed TTFC switch through the statistical information displayed by the host computer software and the data captured by the FC protocol analyzer software.