Research And Design Of Wake-up Technology With High Sensitivity And Low Power Consumption

In wireless communication systems such as wireless sensor networks and cellular Internet of Things,intelligent,multi-functional,lightweight,miniaturized,low-power,and low-cost features have become the main development direction of communication terminal nodes.How to effectively reduce the average power consumption of the system and increase the on-duty working time has become a difficult and hot spot in the research of Io T terminal nodes.By adopting the sleep and wake-up low-power mechanism,the Io T terminal nodes automatically enters a deep sleep state when idle,and the terminal node enters the working state through radio frequency wake-up.In the deep sleep state,the terminal node can detect the radio frequency wake-up signal with near-zero power consumption,achieving efficient and intelligent energy management.This thesis carries out the research and design implementation of key technologies of RF detection wake-up receiver with high sensitivity,large dynamic range and low power consumption,and the main work is as follows:1.Firstly,various RF wake-up receiver architectures at home and abroad were investigated,and the working mechanisms and characteristics of each architecture were compared.Furthermore,the technical methods of improving the receiving sensitivity of the wake-up circuit were studied and analyzed,and the working principle of RF envelope detection circuit was theoretically analyzed.2.The design optimization and performance simulation of the antenna and detection receiving circuit of the RF wake-up receiver were carried out by using HFSS,ADS and other simulation software;The USRP software-defined radio platform was used to design the waveform and data frame structure of the RF wake-up signal to provide the signal source input for the RF wake-up receiver.3.A multi-channel wake-up receiver system technical solution is proposed,which adopts signal pre-frequency shifting,two-stage detection,and band-pass filtering methods to achieve multi-channel parallel wake-up;ICE40UP5K FPGA is used for signal synchronization,matched filtering,sampling decision,and other baseband signal processing designs,and the corresponding computing processing power consumption is less than 0.5mW.4.An experimental verification platform for RF wake-up receiver was built,and the main performance indicators of the receiver circuit were tested and analyzed,the receiving sensitivity of the single-stage detection circuit reached-58 dBm,and the wakeup sensitivity reached-92 dBm after cascading low-power LNA,and the RF wake-up signal input dynamic range reached 71 dB by using drain peak shaving,multi-channel heterogeneous detection receiving methods.The RF detection wake-up receiver system designed in this thesis has the characteristics of high sensitivity,large dynamic range,low power consumption,and simple structure.It can be widely integrated and applied in low-power,long-life Io T terminal systems such as wireless multi-source sensors,active sensing RFID tags,and situation awareness monitoring nodes,and has good engineering reference value.