Design And Implementation Of High-Energy Image Signal Processing Core Based On Nonvolatile Memory

Image Signal Processor(ISP)is an important application specific integrated circuit for digital camera imaging.Digital cameras use photosensitive sensors to record images of nature.During this process,ISPs need to digitize the perceived real image information before it is processed and stored by the digital system.With the development of the Internet of Things,the demand for high energy efficiency in edge camera devices is increasing,and the process of ISP processing involves the movement of a large amount of digital information,which poses a great challenge to low-power design.In recent years,Compute in Memory(CIM)has been proposed to overcome the power bottleneck caused by data movement,computation and re-movement in the Von Neumann architecture by directly executing computational processing in memory.In memory computing greatly reduces the data movement involved in data operations,reduces the number of clock cycles required for multiplication and addition operations,and achieves high parallelism in computing.In particular,the emergence of Non-volatile Compute in Memory(nvCIM)based on Resistive Random Access Memory(RRAM)has brought new changes to in memory computing and memory structures due to its advantages such as non-volatility,large capacity,scalability,low power consumption,and low access latency.Firstly,the research background and significance of ISP and nvCIM is elaborated on,and their current development status is introduced in this thesis.An improvement plan for nvCIM and ISP is proposed: utilizing the low power consumption and accelerated computing of nvCIM to achieve a high-efficient non-volatile memory image signal processing core nvCIM-ISP.Secondly,existing ISP algorithms to introduce nvCIM for calculation and make adaptive pixel quantization is proposed in this thesis.Based on the analysis of ISP image processing algorithm theory,a low precision quantization image signal processing algorithm is proposed to minimize data interaction with off-chip memory and make improvements for adaptive in memory computing.Finally,the pipeline structure was utilized to improve parallel processing speed,improve the circuit structure of the processing module,and implement the ISP image processing module.On the other hand,by studying the principles of nvCIM,analyzing the structure of nvCIM,a nvCIM Macro based on RRAM is implemented,which solves the problem of overload current and high delay in nvCIM in the past and improves energy efficiency.The nvCIM Macro designed in this thesis based on RRAM can complete 8-bit input8-bit weight multiplication and addition operations under 0.8V power supply,and ultimately output 19 bit results,with a processing circuit delay time of 0.76ns/b.The digital front-end image signal is stored and processed by multiplication and addition based on this Macro,and the intermediate results are then processed by the image signal processing module to output the final image.After verification of image processing results and performance evaluation comparison,the nvCIM-ISP implemented in this thesis meets the high energy efficiency requirements of edge digital image signal processing related applications.