Optimizations For Performance,energy,and Lifetime On Non-volatile Memory Based System

With the development of multi-core systems,the demand for memory capacity is increasing.These systems can execute multiple parallel programs,which results in a large aggregate working set size in memory.At the same time,as technology develops to 10 nm,it is difficult for traditional DRAM and SRAM technologies to scale down to smaller cells due to limitations such as capacitor placements,device leakages,and charge sensing.Thus,researchers are looking for replacements for conventional memories.Emerging non-volatile memory technologies,such as Phase Change Memory(PCM),and Spin Transfer Torque Random Access Memory(STT-RAM),has emerged as promising alternatives.Non-volatile memory technologies have many attractive advantages,such as non-volatile,low energy,byte-addressable,low latency,high density and scalability.However,they are limited by high write latency and energy,and poor lifetime.To solve these problems,this dissertation focuses on improving the performance,energy and lifetime of non-volatile memory.Specifically,we use PCM as main memory,and STT-RAM as cache memory.The main contributions are listed as follow.(1)Peak-to-average pumping efficiency improvement for charge pump in phase change memories.The pumping efficiency of a PCM chip is a concave function of the write current.Based on the characteristics of the concave function,the overall pumping efficiency can be improved if the write currents are uniform.In this paper,we propose the peak to-average(PTA)write scheme,which smooths the write current fluctuation by regrouping write units.Thus,the overall pumping efficiency is improved,and the write energy is reduced.(2)Write reconstruction for write throughput improvement on MLC PCM based main memory.The write latencies of different cell state transitions in MLC PCM range significantly.When cells are concurrently written in the burst mode,the write latency of a burst is delayed by the worst state transitions.To improve the write throughput,we propose a Write Reconstruction(WR)scheme.WR reconstructs multiple burst writes targeting the same memory row,where the worst case cells are grouped together at some writes.With this approach,the write latency of other writes will be reduced.(3)Two-step state transition minimization for performance,energy,and lifetime improvement on MLC STT-RAM.Two-step state transitions would significantly impact the lifetime of MLC STT-RAM due to the wasted flips in the soft domains.To solve the problem,we propose a novel two-step state transition minimization(TSTM)scheme,to improve the lifetime of MLC STT-RAM when it is employed in cache design.The basic idea is by sacrificing certain cells as auxiliary flags,the two-step state transitions in STT-RAM can be well eliminated.Thus the performance,energy,and lifetime are improved.(4)Accurate age counter for wear leveling on non-volatile based main memory.Conventional age counter is not able to accurately represent the real wearing.The existing wear-leveling methods are limited for extending the lifetime of NVM.To address these problems,we propose an accurate age counter increment mechanism,which is designed with the awareness of flags overlap between the write buffer and physical NVM unit.Cooperating with the proposed age counter,we develop an accurate age counter-aware wear leveling for non-volatile based main memory to further improve the lifetime.We evaluate the effectiveness of the techniques on our simulation platform.Experimental results show that the proposed techniques can reduce the write energy of PCM,improve the write throughput of MLC PCM,improve the performance,energy and lifetime of MLC STT-RAM,and improve the accuracy of age counter and effectiveness of wear-leveling.