Exploring Wear Leveling And Optimization Techniques Of Non-Volatile Memory

With the development of embedded technology, embedded systems have been widely applied in many fields, such as cloud computing, internet of things and big data.However, embedded system applications trend that require more capacity and bandwidth, which presents new challenges for the traditional DRAM-based memory system. At the same time, DRAM technology limits its energy, scalability and reliability.Fortunately, emerging non-volatile memory technology, such as Phase Change Memory,has emerged as a promising alternative to DRAM for the above dilemmas. It has many attractive advantages, such as non-volatile, low energy, byte-addressable, low latency,high density and scalability. Nevertheless, new non-volatile memory has some constraints including low endurance and the poor performance of multiple-levels cell(MLC), which proposes challenges for its management.To address the above issues, considering the program-specific features of embedded systems, this thesis firstly studies the lifetime of emerging non-volatile memory. Then,we study the poor performance of MLC mode in morphable non-volatile memory. After that, combining with the emerging non-volatile memory, we study the memory management in mobile virtualization. The main contributions are listed as follow.(1)A program in embedded systems usually distributes write traffic in an extremely unbalanced way, which could further decrease the lifetime of emerging non-volatile memory. Combining with the program-specific features, this thesis proposes a space-based wear leveling in software compiler level to produce optimal space allocation and address assignment for each variable, so that we can use a limited size of unoccupied space on emerging non-volatile memory for achieving a balanced write distribution and improving the lifetime of emerging non-volatile memory. The basic idea is to extend frequently written variables into specific-sized arrays, and evenly distribute writes on allocated array.(2)Emerging non-volatile memory cell usually can be dynamically programmed to be in either multiple-level cell(MLC) mode or single-level cell(SLC) mode. Compared to its SLC counterpart, MLC can achieve the high density and larger capacity, but limits high latency and low endurance. To address this issue, we propose a morphable memory wear leveling, which dynamically determines the size of SLC/MLC space in new non-volatile memory according to different workloads of each region in program, andassigns an optimal address for each variable. The basic idea is to allocate low-latency SLC and high-density MLC cells for write intensive variables and other ordinary variables, respectively.(3)Virtualization offers significant benefits, such as better isolation and security for embedded systems. However, the limited amount of memory and virtualization's memory-demanding nature make it challenging to virtualize embedded systems efficiently. To address this issues, a simple and effective page management technique,named Balloonfish, is proposed to convert the memory cell state between multi-level and single-level for achieving a balance between performance and memory space. The basic idea is to allocate low-latency SLC cells for heavily accessed active pages and store other inactive pages in high-density MLC cells.Our evaluation based on Simplescalar simulator and Samsung Exynos 5250 SoC shows that: 1) the space-based wear leveling effectively prolongs the lifetime of emerging non-volatile memory with a low memory overhead; 2) the performance and lifetime of the morphable memory are effectively improved; 3) Balloonfish achieves28.63% performance improvement compared with the baseline scheme. Finally, we expect this work can serve as a first step toward the full exploration of application-specific in emerging non-volatile memory for embedded systems.