Study On Device And System Of Emerging Non-Volatile Memories

Emerging Non-Volatile Memory( NVM), which is usually represented by Ferroelectric Random Access Memory(FRAM), Phase Change Memory(PCM), Magnetic Random Access Memory(MRAM) and Resistive Random Access Memory(RRAM), is considered as the next generation semiconductor memory for its advantages in high write/read speed, low power consumption and high storage density. This paper studies on the design techniques of memory cell and power consumption optimization of emerging non-volatile memories.Firstly, this paper studies on the design techniques of read/write circuit module and interface circuit module. Based on the operating characteristics of NVM, an analysis and summary of read/write circuit module on the design techniques is presented. Then, the interface circuit module is discussed and some interface circuit design methods are proposed.Secondly, multi-level-cell of NVM is discussed and a new 2 Transistors 1 Magnetic Tunnel Junctions(2T1MTJs) memory cell is proposed to reduce the extra write current and power on the soft bit in MTJ device. To demonstrate the functions of the new memory cell, operating principle of the new memory cell is discussed in detail, besides, a necessary simulation using 45 nm low power COMS technology of Predictive Technology Model(PTM) is carried out. According to the simulation results, the write current and power can be reduced at least 50% and 72% respectively.Lastly, this paper discusses the optimization of power consumption. Focused on the coding technique, after discussed a reportorial method, an improved method is proposed to improve the reliability of read process. To verify the effect of improved method, a simulation is designed. According to the simulation results, this improved method can gain reliability of read process with acceptable degeneration of power consumption optimization.