| With the development of communication rate,metal interconnection has prominent disadvantages in distance,bandwidth and power consumption.Optical interconnection has the characteristics of low loss,large bandwidth and high energy efficiency."Optical advance and copper retreat"is the research hotspot of high-speed communication.Optical receiver is mainly composed of optical detector chip and transimpedance amplifier（TIA）chip,the latter determines the optical receiver bandwidth,sensitivity and power consumption,is the core component of optical communication module.The existing TIA chips are mostly implemented by Ga As or Si Ge process,which has high power consumption and low integration.In this paper,for the application of optical interconnection in 400G data center,the key circuit design technology of high-speed TIA under standard CMOS process is studied,as well as the photoelectric cooperative hybrid integration technology with silicon photonics photodetector.Academic contributions of this paper include:First,to meet the requirements of digital low-voltage CMOS process and multi-channel high density integration,a transimpedance front-end circuit with a type of inverter structure is proposed,which uses single-ended architecture to achieve transconductance doubling by multiplexing current,and combines ultra-wideband power supply voltage regulation technology to achieve high integration,low power consumption and high signal integrity.Secondly,to meet the requirements of hybrid integration of silicon photonics photodetector,an optoelectronic co-design frequency peaky technology is proposed.The inductors and T-Coil on the chip are custom-designed and distributed at several key nodes to offset the high frequency loss of the parasitic capacitor,thus significantly increasing the bandwidth of TIA circuit.Third,a linear TIA chip is designed and implemented based on 28nm CMOS process.The measurement results show that the-3dB-bandwidth of the chip reaches35 GHz,and the linear transimpedance gain covers 46-66 dBΩ.The channel data rate is up to 112 Gb/s,and the PAM-4 eye diagram is obtained.Fourthly,an amplitude-limiting TIA chip was designed and implemented based on 45nm CMOS process,and the optical receiver was constructed by hybrid integration with silicon photonics photodetector.The measurement results show that the-3dB-bandwidth of TIA reaches 23 GHz and the maximum transimpedance gain is53 dBΩ.At the lowest optical modulation amplitude of-7.7 dBm,the optical receiver can realize the NRZ modulation of 50 Gb/s single channel rate and the bit error rate below 10-12,and the clear PAM-4 eye diagram of up to 100 Gb/s.Fifthly,in view of the requirement of 800G data center optical interconnection for single channel 200 Gb/s circuit,the ultimate bandwidth performance of TIA circuit under 28nm CMOS process was explored,and the TIA circuit with single channel 224Gb/s data rate was designed,and a clear PAM-4 eye diagram was obtained by simulation at this rate. |
