Research And Design Of High Performance Sigma-Delta Modulator

Analog-to-Digital Converter(ADC)is a critical devices that convert continuoustime analog signals into digital signals.In modern technology and industry,the importance of ADC is self-evident.They can convert various physical quantities in the real world,such as temperature,pressure,voltage,and current,into digital signals,thus facilitating data processing,transmission,and storage.The Sigma-Delta ADC is a highprecision and low-power ADC design scheme that can significantly reduce the impact of analog device mismatches and improve the accuracy of ADC by increasing the sampling frequency and shaping the in-band quantization noise.In the design of SigmaDelta ADC,the design of the modulator is a key and difficult point.This thesis takes high-performance Sigma-Delta modulator as the topic,and mainly conducts in-depth research from two aspects: high precision and low power consumption.The main work is as follows:The analysis of Sigma-Delta modulators with different architectures is carried out.The MASH2-2 structure is adopted to ensure the stability of the modulator.The double sampling technology is used to design the first integrator to improve the sampling accuracy and reduce power consumption.The chopping stabilization technology is used to reduce the impact of flicker noise and mismatch errors on the first integrator.The Sigma-Delta modulator under non-ideal conditions is systematically modeled and simulated in the Matlab Simulink environment,and the expected performance indicators of each submodule are obtained based on the simulation results,which provide guidance for circuit-level design.The modulator circuit is designed and pre-simulated.The layout of the modulator is designed and post-simulated.0.35 um CMOS process is used to design the modulator circuit,the power supply voltage is 5V,and the sampling frequency is 2.56 MHz.The simulation results show that the signal-to-noise and distortion ratio of the modulator reaches 119.6dB,the effective number of bits reaches 19.57 bits,and the overall circuit power consumption is 26.7mW,which basically meets the design requirements.