Design Of RISC-V Memory Hardware Isolation

As an emerging open source reduced instruction set,the share of RISC-V in the microprocessor market is increasing year by year,due to its lake of security isolation mechanism at the hardware level,how to ensure the security of the microprocessor has become an urgent problem.Aiming at the security problem of RISC-V,this paper has made the following improvements:(1)Similar to the mainstream hardware isolation mechanism,the security state of the processor is divided into the Secure World and Normal World,and the memory is divided into the secure region and the non-secure region.The Secure World can access both the secure region and the non-secure region,while the Normal World can only access the non-secure region.(2)In this design,the security partition of memory has be solidified by hardware to prevent the leakage of security data;At the same time,this design divides the memory by address range to simplify the judgement logic of security permission.(3)This paper proposes a new security exception detection methods FSEDM(Fast Security Exception Detection Methods),which can detect security exceptions faster.Without using the virtual memory system,the security exception will be detected in the Execute Stage for pipeline,and the corresponding memory access operation will be ignored,so as to improve the security of resource isolation;In the case of using virtual memory system,security exception will be detected after one period of requestor for memory access,and the request will be canceled.This new method can detect security exception 1-6 clock cycles ahead of the traditional methods,providing a more effective safety isolation protection for the processor.This design uses Chisel to complete the development on the agile development platform Chipyard,and is tested and verified through the tools provided by the platform.