Research And Implementation Of Parallel MSD Adder Based On FPGA

In the era of rapid development of computers,with the continuous improvement of computing power and speed of electronic computers,adders play a crucial role.As the basic component of arithmetic operation,adders can not only be used for conventional arithmetic operations,but also for counting and address operations.However,the traditional binary adder has been plagued by carry problem,which has always constrained the operation speed and performance of the adder.How to reduce the carry delay and improve the speed of the adder has always been a research focus in the field of adders.This paper studies parallel MSD(modified signed digit)adder,which uses signed redundant binary digits to eliminate carry chain propagation,so as to achieve the purpose of data bit by bit parallel addition.This parallel MSD adder has faster computing speed and consumes less logic gate resources.This paper first outlines the basic principle of the reconfigurable multivalued logic operator,and then describes in detail the design principle of the reconfigurable parallel MSD adder based on the reconfigurable ternary logic operator,as well as the design principle of a special parallel MSD adder that can save more logic gate resources.Then,this paper studies the method of implementing the above two parallel MSD adders on FPGA,designs a modular implementation framework,and implements five different bit-width reconfigurable parallel MSD adders and special parallel MSD adders on Xilinx’s AX7Z020 development board: 32-bit,64-bit,128-bit,256-bit,512-bit.Finally,this paper verifies the correctness of the two parallel MSD adders,and analyzes the speed and resource occupation under different bit-width conditions.In this paper,three classical parallel prefix adders anad a carry free binary SD(signed digit)addition algorithm are also implemented on FPGA.Through comparison of parallel MSD adders,parallel prefix adders and the binary SD addition algorithm,the following conclusions are drawn:(1)The speed of parallel MSD adder is independent of the number of bits,and parallel MSD adder has significant advantages over parallel prefix adder in speed.(2)Among the SD class adders/algorithms,the special parallel MSD adder has a significant advantage in the consumption of logic gate resources.It uses less logic gate resources than the reconfigurable parallel MSD adder and binary SD addition algorithm.The innovation of this paper lies in the design and implementation of a reconfigurable ternary logic electronic processor on FPGA,and on this basis,the design and implementation of a reconfigurable parallel MSD adder and a special parallel MSD adder,which verifies the feasibility of building a parallel MSD adder theory using a reconfigurable ternary logic processor,as well as the high speed of the parallel MSD adder.This paper is helpful to promote the application of parallel MSD adder in traditional integrated circuits and multivalued electronic processors,and is expected to promote the application and development of reconfigurable multivalued logic electronic processors.