A 3T1R1C Nonvolatile Memory Structure That Can Improve Resistance Fluctuation

In recent years,with the advancement of the research in the field of AI represented by machine learning,people have put forward higher requirements for the storage capacity and computing speed of data.The traditional von Neumann architecture needs to frequently move the data between the storage module and the computing module,which will limit the computing speed of the CPU and reduce the energy efficiency.To break through the von Neumann bottleneck,in-memory computing is proposed.SRAM in-memory computing is a relatively mature technology at present,but the data stored in SRAM structure has the risk of power loss.Due to the advantages of nonvolatile data storage,high integration,and low power consumption,the combination of RRAM and logic operation can not only break through the von Neumann structure but also solve the problem of power loss data in SRAM memory structure.Firstly,this paper introduces the traditional 1T1 R unit structure,which realizes the "and" operation through the bus capacitance and unit RRAM and realizes the quantization function through the synchronization of the capacitance on the bus.To overcome the above problems of 1T1 R,we propose a 3T1R1 C structure based on RRAM,which can realize two modes of data writing by using capacitor C and RRAM respectively according to different emphasis on data reading and writing speed and data security operation requirements.After the data is written into the capacitor,the data can also be backed up from the capacitor C to the RRAM through the control signal.The structure combines the unit capacitance C and RRAM,the capacitance is discharged through RRAM,and the units are isolated from each other to realize the "and" operation,which has good linearity.Quantization is realized by charge sharing between the capacitance in the calculation unit and the capacitance on the bus.Compared with the traditional 1T1 R unit,this structure is less affected by the fluctuation of RRAM resistance;At the same time,the three-state addressing function can be realized by combining two3T1R1 C units on a column;By combining two adjacent columns of 3T1R1 C cells,the values of sum and cost can be calculated in parallel,and the calculation results of half adder can be expressed by the voltage on the bus capacitor.Finally,the 3T1R1 C structure is simulated and analyzed.Taking 64 units as an example,the linearity difference of the 3T1R1 C structure is about 1% of that of the 1T1 R structure.Taking a column of 64 cells as an example,the power consumption of the 1T1 R structure is about 44.06% of that of the 3T1R1 C structure.Through1000 Monte Carlo simulations,the average delay of set and reset operation of the 3T1 RC unit is obtained.The functions of three state addressing and half adder are verified.