Design Of Convolution Macro For Storage Computing Based On RRAM Array

At present,the application of intelligent devices based on various neural network algorithms has penetrated into all walks of life,which requires a huge amount of calculation and storage as support,but the hardware platform resources to provide neural network edge computing are always limited.On the one hand,convolution operation in neural network is more complex,which requires tens of billions of computation and hundreds of megabytes of parameter storage in a single recognition,accounting for more than 90% of the total computation;On the other hand,most of the existing neural network edge computing processors are based on CMOS technology and von Neumann architecture,and a large amount of data movement between memory and computing unit brings high energy consumption and high delay.At the same time,it faces the physical limit of manufacturing process.The new RRAM can complete the basic product sum calculation of convolution process while storing data.It has high integration and non-volatile compatible with CMOS technology,which provides a hardware implementation basis for solving this problem.Based on the above background,this paper designs a 2T2R-RRAM storage computing convolution macro.The whole processing unit is composed of RRAM storage array and peripheral circuit: 9×8 bit units with 2T2 R structure are cross connected to form RRAM storage array,and the word line signal generation module WL,bit line signal generation module BL and the corresponding source line signal generation module SL form peripheral circuit.The processing unit can be operated in two modes: the memory mode is used to store convolution weights,and the memory calculation mode is used for convolution calculation.2T2R-RRAM storage calculation convolution macro can complete the convolution operation in the convolution layer of the convolution neural network customized in this paper,and finally realize feature extraction by using eight 3×3 convolution check input matrix.Based on cadence and FPGA,the product sum calculation time of 50 ns is achieved,the accuracy is 96.96% on MNIST database,and the peak energy efficiency is58.82 tops/W,compared with the previous work,it achieves higher hardware calculation accuracy,higher reading / calculation speed and lower power consumption.