| With the commercialization of the 5th Generation Mobile Communication(5G)technology on a global scale,the importance of mobile communication network testing technology which is the most critical part of the communication industry has increased significantly,and the demand for communication network testing instruments has increased significantly.The research and development of 5G road testers plays a key role in improving the 5G communication network test system and provides reliable guarantee for the planning,construction and operation of mobile communication networks.Relying on Chongqing’s major theme project "R&D and Application of 5G Drive Test Instruments" and 5G system protocol standards,this thesis has studied and designed the 5G drive tester physical downlink shared channel(PDSCH)de-resource mapping and channel estimation algorithm scheme,and the hardware implementation is implemented by using a field programmable gate array(FPGA)The specific research contents are as follows:1.The demodulation reference signal(DMRS)generation method in the PDSCH deresource mapping process is studied.Aiming at the problem of time wasting of pseudorandom sequence generation caused by fixed state offset,a fast sequence generation method for constructing a state transition matrix is proposed,which can effectively reduce the time consumption of hardware implementation.Aiming at the problem of repeated calculation in solving the symbol conflict in the traditional PDSCH data resource extraction method,a resource extraction scheme based on time-frequency domain bitmap is proposed.The bitmap is used to directly locate the position of PDSCH data resources in the timefrequency domain,and skip cases occupied by other symbols.2.The channel estimation algorithm that meets the requirements of the project is designed.Combined with the comprehensive consideration of algorithm performance and hardware implementation complexity,the channel estimation algorithm based on Discrete Fourier Transform(DFT)is adopted.There is the problem of energy leakage,and an improved method is proposed.Firstly,the average signal-to-noise ratio of the system is estimated by using the DMRS signal.On the basis of the Least-Square(LS)algorithm,the noise is estimated by adding a window in the frequency domain and correcting the timedomain noise estimation interval with the help of the average signal-to-noise ratio.The average power is converted into the threshold noise reduction threshold in the cyclic prefix for noise reduction operation.The simulation results show that the improved algorithm can effectively reduce the influence of energy leakage in the non-sampling interval channel.3.Design the FPGA hardware for the proposed algorithm,based on the modular idea of the whole and then the part,first design the overall frame of the solution resource mapping and channel estimation,and then design each sub-module in detail.A bitmapbased method is used to quickly extract PDSCH data resources,and a parallel pipeline method is used to improve the efficiency of DMRS sequence generation and reduce the delay of channel estimation.4.Use Vivado and Modi Sim software to simulate the function of the hardware design part,test the correctness of the data according to the output waveform,and compare the simulation output results of MATLAB and Modi Sim to complete the result accuracy verification.The overall test is carried out on the premise of correct simulation results and reasonable resource occupation to verify the feasibility of the algorithm and hardware design. |
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