Research And Design Of Memory Computing Circuit For Convolutional Neural Network Based On RRAM

With the rapid development of the artificial intelligence industry,intelligent devices with neural network algorithms as the core have begun to be applied on a large scale,but at the same time,it has also brought the demand for computing on massive data.Due to the separation of computing and storage units in the traditional Von Neumann computing architecture based on CMOS(Complementary Metal Oxide Semiconductor)devices,it is easy to encounter the bottleneck of"power wall"and"storage wall"when processing big data,which is more and more difficult to meet new computing needs.However,the"computing in memory"structure can directly perform operations on the storage,avoiding the power consumption and computing power loss caused by frequent data transfer from storage to computing units,which is an efficient approach to breakthrough this bottleneck.Resistive Random Access Memory(RRAM),as a new type of memory device,has the characteristics of high speed,low power consumption and non-volatile,and can realize efficient in-memory operations in a specific array structure.Aiming at the computing requirements of convolutional neural networks,this paper designs a digital RRAM in-memory computing architecture and its peripheral circuits and control systems based on the RRAM storage array.The main work and innovations are as follows:(1)Research the resistance switching principle,array structure,typical I-V characteristics of oxide-based bipolar RRAM devices,and non-ideal factors of current RRAM devices,and design the Verilog model of RRAM for simulation according to its simple mathematical and physical model.(2)Combined with the array structure of 1T1R,the algorithm principle of in-memory computing based on RRAM is studied.According to the shortcomings of low calculation accuracy of analog or multi-level RRAM devices,a digital RRAM device calculation scheme and a matching method for mapping weights and conductances are proposed.Each RRAM cell only represents a digital quantity of 0 or 1,and multiple cells are divided into positive and negative.The two groups together represent a weight,and the calculated current is shifted and added by an ADC(Analog-to-Digital Converter)to obtain the final result.The scheme reduces the reliability requirements for RRAM devices and improves the calculation accuracy at the same time.(3)Use Python to build neural network models of different sizes,and design quantization algorithms to quantize the model weights into 8bit,5bit,4bit and 3bit.At the same time,the inter layer input is quantized into 8bit,4bit,3bit and 2bit.Select the model suitable for deployment according to the accuracy and the number of parameters,and optimize the algorithm in combination with hardware to balance the calculation accuracy and resource consumption.(4)The RRAM in memory computing system and digital control circuit are designed to complete the basic functions of reading,writing and in memory computing.It includes instruction system and decoding,basic read-write state machine,design of RRAM in memory computing core,mapping storage scheme of weight and bias,intermediate data cache scheme,timing,data flow and state machine of in memory computing,and completes its RTL code design.The correctness of the design is verified according to the simulation waveform,and DC synthesis is carried out to evaluate the basic performance of the circuit design.The circuit design is based on the characteristics of Hf O_x-based RRAM,using Tensor Flow2.4.1 version to model the neural network,quantizing and testing the model with different precisions according to the quantization function of the algorithm.As a result,the recognition accuracy of 95.39%is realized on MNIST handwritten numeral set under the condition of unsigned 4bit inter layer input and signed 5bit weight.At the same time,the above circuit is designed based on the Verilog,and is simulated and synthesized by EDA tools such as VCS and DC.Compared with the traditional AI chip,it reduces a lot of multiplication,adder and cache resources,and achieves the throughout of 7.57GOPS with an area of about 0.084mm~2.It is estimated that it takes 7.72μs to recognize a picture of handwritten digits.