A Run-time Reconfigurable Simulation Verification Platform For QC-LDPC Code Based On FPGA-Upper Computer

Channel codes plays an important role in communication and storage systems because it can counteract the interference of information transmission process and help the destination receive correct information.QC-LDPC codes have been widely used in various communica-tion standards and industrial products due to their strong error correction performance,low decoding complexity and easy structure for practical engineering implementation.In different usage scenarios,there are different requirements for performance,delay,resource consumption and other indicators,so the type of QC-LDPC code used and the internal set-tings of the decoder are also different.In order to quickly evaluate the performance of a given code and analyse its hardware decoding performance under different parameters,aiming at the lack of flexibility in the current hardware test system and the low test rate in the software test system,a run-time reconfigurable simulation verification platform for QC-LDPC code based on FPGA-upper computer is designed and implemented in this thesis.It has the high flexibility of similar software simulation while doing high-speed test.This thesis compiles the upper computer software based on Python language to realize the graphical operation of the platform,the printing and display of simulation data and the drawing of performance curve.The FPGA part of the simulation verification platform is implemented based on Xilinx VCU118 evaluation platform,including seven modules:all zero source-BPSK modulation-AWGN channel-demodulation（quantization）-decoding-error statistics and control.The channel is the interference source in the test system,and its accu-racy is very important for the accuracy of decoding performance test.Based on Box-Muller algorithm,a highly accurate additive gaussian white noise generator is realized on FPGA by using linear fitting method,which can realize the range of-10～40d B(_（7）/0and the ac-curacy of 0.05d B.A single noise module generates two noise data per clock.The test system requires a total of 64 noise modules.The consumption of LUT,BRAM and DSP resources accounts for 5.1%,17.8%and 22.5%of the evaluation platform resources respectively.The decoder is the key of the simulation platform to test different QC-LDPC codes.This the-sis designs and implements a highly flexible decoder,which can configure code information,matrix information and decoding parameters at runtime to support the flexible decoding of most QC-LDPC codes.The decoder adopts partial parallel architecture,which can take into account the requirements of flexibility,resource consumption and throughput.At the same time,decoding uses block parallel method with a maximum parallel degree designed of 512.In the designed decoder structure,it can not only complete the decoding of codes with dif-ferent structures,but also be compatible with two message passing algorithms of TDMP（Turbo-Decoding Message-Passing）and TPMP（Two-Phase Message-Passing）algorithms.The hybrid min-sum algorithm is used to test the influence of different normalization factors and offset factors on decoding performance.Also,the decoder can perform iterative early stopping to improve throughput.Through the logical shift before and after decoding,the support for codes with puncturing and shortening and check matrix with less than rank is realized.The FPGA part of the simulation verification platform consumes LUT,BRAM and DSP re-sources,accounting for 55.03%,62.82%and 26.55%of the evaluation platform resources respectively.With the parallel computing ability of FPGA and the early stop mechanism of decoding iteration,the platform can reach the test rate of Gbps at the highest.After test and comparison,the hardware simulation speed can reach 1000 times of the software simulation speed,which significantly reduces the simulation time.Through the highly compatible and general structure designed internally,the check matrix information and other decoding con-trol information of various QC-LDPC codes such as 5G,DVB-S2 and Wi Fi,as well as many decoding parameters such as offset factor,normalization factor,bit width and maximum it-erations are configured in real time through the graphical interface of the upper computer,which realizes the reconfigurable platform at runtime and has a high degree of flexibility sim-ilar to computer software simulation.In the later stage,according to the parametric design,the flexible decoder for testing can be quickly and conveniently transformed into a special decoder for practical engineering application,so as to realize the transformation from testing to application.