The Technology Of Design For Test Of Dynamically Configurable Multi-Die Based On TAP Controller Architecture

With the development of Moore’s Law,the manufacturing cost of chips has become higher and higher,and process improvement has become more and more difficult.A technology of multi-die integration emerges as the times require.However,this integration technology brings many problems in the testing field,such as insufficient chip package ports,and the test interconnection between die leads to the mutual influence of die tests.Therefore,for the integration of multi-die,it is necessary to design a design-for-test method to ensure the independence of multi-die testing and reduce the requirement of test ports.Based on the above requirements,this paper proposes a technology of design for Test of dynamically configurable multi-die based on TAP Controller Architecture(TAP CA).The TAP CA includes a TAP state machine controller module,an instruction register module and a test data register module.TAP CA is used to control the memory test module and scan test module of each die,and finally realize the enable operation and test operation of the memory and scan circuit of the multi-die.For multi-die memory testing:TAP CA-based memory test modules include JTAG control modules,test circuit conversion modules and IEEE 1687 circuits.Firstly,the TAP state machine controller is used to control the instruction register,and the corresponding test data register is controlled by the instruction register,so as to realize the dynamic configuration of the test data register.The JTAG input module is controlled by the test data register to complete the start-up operation of the die to be tested.The TAP state machine inside the TAP CA is used to generate the mode signal,and the test circuit conversion module is controlled by the mode signal to realize the control of the state signal of the IEEE 1687 circuit in the integrated die by the TAP CA,and finally the memory test of the die is completed through the IEEE 1687 circuit.At the same time,the test data register also controls the JTAG output module,and the result of the testing is output to the tdo port of the die for observation.For multi-die scan test:The scan test module based on TAP CA includes a scan test input control module and a scan test path control module.First complete the scanning test and generate the test protocol file,write the configuration value of the TAP CA module into the initialization file of the protocol through the test protocol file,and form a controllable test data register module after reading the initialization file.The scan test path control module is controlled by the test data register module to select the tested die,and the scan test input control module is controlled to enable the scan test input of the selected die.Finally,the test vector is shifted and captured into the scan chain to realize the scan test of the die,and the result of the scan test is output to the scan output port of the die for observation.In this paper,three dies are designed based on TSMC’s 180nm process as a test platform,and the proposed"the technology of design for Test of dynamically configurable multi-die based on TAP Controller Architecture(TAP CA)"is simulated and verified.The results show that the designed TAP CA circuit can be used as a shared module,the shared module implement the memory test and scan test of the die in series one by one,ensuring the independence of the tests between the die.The memory test of multiple dies can be realized through the 5 JTAG test ports outside the chip,and the scan test of all dies can be realized through the 6 necessary scan test ports outside the chip.The circuit area of TAP CA is only 12085.517μm~2,and TAP CA accounts for 2.24m W in the whole test power consumption,which proves the feasibility of this technology.