Research On VLSI Low Power Testing Technology

The complexity of current generation ICs, combined with rapidly developing high density, high speed packaging and reduced design cycle time, has made it extremely difficult and expensive to comprehensively test electronic systems, and diagnose failed parts using traditional methods. This situation worsens as we move toward nanometer technologies.The reduced device geometries, increased operating speed and very low power supply levels, are reducing noise margins and component reliability, complicating defect behavior and increasing the impact of timing, cross talk, transient, and other spurious faults. Power consumption during normal operation and test application becoming increasingly important, low power design only address power dissipation during normal operation. Moreover power consumption during test application must be taken into consideration. Therefore, there is a great need for innovative advances in test and diagnosis methodologies to cope with these problems. In this dissertation, we present some original ideas for problems above.Boolean process based waveform simulator is provided. We use universal media circuit format (UMCF) to build universal experimental platform. Then convert ISCAS85 and ISCAS89 to UMCF. So it can build experimental platform independent of specific ISCAS circuit format. Fault simulator is easy implemented using UMCF. Waveform simulator provides not only logic simulation but also timing simulator. So it can be widely used in current ICs testing.Probabilistic study of scan-based testing power consumption is provided. Scan chain power contribute mainly to whole test power during scan testing. Because test vectors shift into CUTs and shift out all by scan chain. A statistical model of scan power is provided in this dissertation and experiment is carried out to validate the correctness of this model. Using this model we can estimate scan chain power and further used to find optimal test vector or scan cell order for minimizing power during scan testing.The detail analysis of low power BIST is provided. Except during external testing, but also during BIST, test power problems must be copped with correctly. Many people have focused on low power BIST research recently. Techniques about low power BIST method are analysized and categorized. Moreover, a case relative application of low power BIST is provided. So in different case we can trade off different parameter and choose the best suitable low power BIST solution.