Design And Implementation Of Scheduler Mechanism And Bus Controller In HINOC2.0 MAC Coprocessor

High Performance Network over Coax(HINOC)is a broadband access solution based on the out-of-band channel of Community Antenna TV(CATV)coaxial cable which can provide users with high-performance duplex information transmission.HINOC technology works on the coaxial cable channel band above 860 MHz,only by adding correlative HINOC Bridge(HB)and HINOC Modem(HM)to the existing cable networks,which could provide the services of IPTV,SDTV/HDTV and surfing the internet.It has great significance for removing restrict of the last 100 meters broadband access network,improving broadband access and accelerating the process of network convergence.This paper is based on a National High Technology Research and Development Program(863 Program)undertaken in our laboratory–“Research and Chip Design of a New Generation of Broadband Access Technology over Coax”.First of all,the analysis of HINOC network and MAC layer protocol is proposed,and the overall implementation scheme of the MAC coprocessor is introduced.Then,the requirements of HINOC2.0 are deeply discussed,and an implementable scheme of memory management module,queue management module and scheduler module which meets the requirements is proposed.Besides,the improved scheme is deeply introduced.Following that,the bus module which meets the new requirement is discussed.At last,the simulation and board-level verification of these modules is also mentioned,which demonstrate the correctness and feasibility of the design and the rationality to achieve the expected goals.