Research And Design Of Anti-Transient Electrical Stress Of Capacitive Isolation Gate Driver Ics

Gate driver ICs are widely used in switching power supplies,solar inverters,industrial motor drives,household appliances and other systems.In order to avoid the danger of leakage of high-voltage circuits in the system to the human body and intelligent control circuits,it is necessary to use isolators to achieve electrical connection between different system modules.Insulation and isolation.In order to reduce system size and cost,more and more companies integrate isolators and gate driver circuits on the same chip,so isolated Gate driver ICs were born.With the rapid development of the wide-bandgap semiconductor industry,Ga N power devices are widely used in various power electronic systems.However,when the system is working,the driver chips of Ga N power devices are often impacted by transient electrical stress,which can easily lead to isolated gates.The driver chip output logic error.In order to achieve higher switching speed and higher operating frequency,the research on anti-transient electrical stress of isolated Gate driver ICs is of great significance.In this thesis,the isolation method and modulation method of the isolated gate driver chip are firstly studied,and the influence of the common mode transient electrical stress on the isolated gate driver chip is analyzed,and then the existing design schemes to improve the common mode transient immunity are studied.Discovering existing designs often requires sacrificing chip power consumption and propagation delay.Aiming at the contradictory relationship between common mode transient immunity and chip power consumption and transmission delay,an overall design scheme of capacitive isolation gate driver chip is proposed.The low-latency demodulation circuits all use a differential symmetrical structure,so that the capacitive isolation gate driver chip has a common-mode transient immunity greater than 50V/ns;the digital filter circuit can detect common-mode transient electrical stress events greater than 50V/ns,and correspondingly generate a control signal to eliminate the envelope signal error caused by the common-mode transient electrical stress.On the premise of not increasing the power consumption of the transmitter and the transmission delay of the chip,the capacitive isolation barrier drives the common-mode transient of the chip.Noise immunity is improved to greater than 200V/ns.In this thesis,based on the 0.25μm BCD process,the design and tape-out of the capacitor isolation gate driver chip are completed,and the parasitic parameters extracted from the designed layout are subjected to post-simulation(due to the epidemic situation and tight production capacity,the tape-out is very slow,and there are no test results for the time being).The post-simulation results show that : The capacitive isolation barrier driver chip designed in this thesis has a common mode transient immunity of 250V/ns,a maximum transmission delay of 19.9ns,a maximum pulse width distortion of 4.0ns,a maximum quiescent current of4.29 m A,and a maximum operating current of 5.58 m A,all satisfying Design specification requirements.