Font Size: a A A

Research On Chip Cache Power Consumption Control Method Of Multicore System

Posted on:2017-02-26Degree:MasterType:Thesis
Country:ChinaCandidate:S LiFull Text:PDF
GTID:2308330485986061Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the advances in integrated circuit technology and the development of computer technology, multi-core processors on a chip is replacing traditional single-core processors became mainstream in the future. However, due to improvement of chip, the power consumption of the chip and larger density, power consumption has become the bottleneck of high performance processor for further development. Cache as the connection between the CPU and the main memory buffer, which plays an important role in the system of data transmission and storage. And because the cache size increased in multicore systems on chip, the proportion of consumption is also growing. Therefore reduce cache power consumption optimization for multicore systems on chip power consumption as a whole have a vital role.This paper starts from the program’s memory properties to optimize the power of on-chip cache. While the program is running in the process through access cache statistics can be divided into access and data access type, and Protocol to access accounted for almost half of them have access to the space. Therefore, we propose a hardware/software codesign cache power management scheme. The programme is based on the existing control voltage-gating technique and caching mechanism improved the recession a controlled programme, the programme can meet the premise of performance constraints, greatly reducing the power consumption of the system.The other hand, the program runs in the process, by tracing the threads of memory access behavior found in some thread-private data is mapped to the off-line drive on the remote address space. Delay to access this feature that led to the increasing network congestion caused by the increase in power consumption of network. Therefore we propose a thread private data address space remapping algorithm, to a certain extent the dual optimization of system performance and power consumption.Finally, in order to verify the validity of this power control scheme, based software Simulator of the programme for the simulation, but also compares and other existing programmes. Simulation results show that the proposed programmes may be loss of performance on your system is lower than 3% conditions, reduce average power consumption of 75%. In addition, the optimized use of multithreading technology on the programme can be further reduced by about 3% network power and 1% of the performance loss.
Keywords/Search Tags:On-Chip Multi-Core System, Cache, Gated-Vdd technology, Multithreading, Memory Access Characteristics
PDF Full Text Request
Related items