Research And Hardware Implementation Of In-Memory Computing Based On NOR Flash

The continuous progress of human production technology is driving the development of society.In the age of the Internet,we are constantly enjoying the convenience brought by hightech.Currently,artificial intelligence(AI)and semiconductor chips seem to have become synonymous with high-tech.ChatGPT has elevated the importance of artificial intelligence and data analysis to a new level,while integrated circuit technology,which carries all this computing pressure,has also broken through the size limit and entered the post-Moore’s Law era.Tasks that are data-intensive,such as ChatGPT,rely on high-speed central processing unit(CPU)and large-capacity memory technology.In the traditional von Neumann architecture,the processing unit and memory unit are separate,and the transmission of high-density data in physical space brings huge expenses.The problem of the "memory wall" arises because the memory unit lags behind the data processing ability of the processor,thereby limiting the overall performance of the computer.Researchers have developed high-bandwidth memory(HBM)and hybrid memory cubes(HMC)technologies to increase the data throughput of memory and minimize the distance between it and the processor.However,the real breakthrough in this bottleneck is the in-memory computing(IMC)technology,which subverts the traditional computer architecture by performing computing tasks in the memory unit,thus eliminating the data transfer process.However,high-performance in-memory computing architecture involves a series of multilevel cooperative optimization designs,such as memory media,in-memory computing arrays,and algorithm architecture.There are still many key issues that need to be gradually overcome,from algorithm theory to hardware verification.Flash memory has mature process technology,high array integration,good reliability,and strong peripheral circuit integration ability.It has great potential for building large-scale high-performance in-memory computing integrated arrays and architectures and has received widespread attention from academia and industry in recent years.The first part of this article focuses on the application of NOR Flash in-memory computing,proposing a new method for logical calculation in NOR Flash arrays,combining stochastic computing(SC)to optimize the image edge detection algorithm.A low-power,highly parallel,and high anti-noise performance image edge detection strategy is designed,and reliability testing and verification are performed based on 65 nm floating-gate(FG)NOR Flash devices.The results show that the proposed in-memory computing fusion solution has a very high tolerance for the relevant parameter drift of the memory device’s reliability.The second part of this article focuses on the design and implementation of the Flash memory in-memory computing integrated hardware platform.First,a memory array test system based on STM32 is designed.By using a circuit board with matrix selection function,which,combined with a semiconductor analyzer,this test system can perform electrical characteristic testing and analysis of any in-memory computing unit in the array.Second,an in-memory computing integrated circuit system is designed based on FPGA,which integrates functions such as signal generation,signal acquisition,and data processing on the board.By combining new circuit structure and logic code solutions,array-level testing and algorithm verification of the in-memory computing architecture can be achieved on the board.In summary,this article combines algorithm optimization design to propose an image edge detection algorithm based on NOR Flash array,which has lower power consumption,higher parallelism,and stronger anti-interference ability than traditional solutions.At the same time,two in-memory computing integrated hardware platform design solutions with different complexity and functionality are presented,which can realize the actual test analysis of inmemory computing algorithms,integrated arrays,and in-memory computing units,providing an important board-level test analysis platform for in-memory computing system design.