Research And Design Of Computing-in-memory

With the advent of the era of big data,the energy efficiency requirements of applications have become higher and higher.Traditionally,most applications have been implemented on the von Neumann architecture.The central processing unit(CPU)and the memory of the von Neumann architecture are independent of each other,and there are lots of data transmissions between them when performing operations.It will cause serious energy consumption,and the bus bandwidth that supports data transmission is limited,which limits the computing speed of the system.The above problem is the famous ”Von Neumann Bottleneck”.In order to break the limitations of the von Neumann architecture,the architecture of Computing-In-Memory(CIM)came into being.It combines the storage units and the computing units,which can not only support general read and write operations,but also support perform calculations in the memory units.So,CIM architecture can reduce a large number of data movements when performing calculations,and improving the energy efficiency of the computing system.The mainstream CIM architecture is mainly based on three types of memory: static random access memory(SRAM),memristor memory,and Flash memory.The read and write speed of SRAM is the fastest,but it only supports single-bit weight storage,which limits its application scenarios.Memristor-type memories have poor robustness properties.Flash memory can support multi-bit weight storage,has high storage density,and has non-volatile storage characteristics,which is suitable for applications that do not require frequent erase operations and write operations.Therefore,in this thesis,the CIM circuit is designed based on ESF3 NOR Flash memory,and it is applied to perform convolution operations in convolutional neural networks.Because the convolution kernel in the convolution operation is generally fixed,it is not necessary to frequently erase and write in the storage array.Moreover,the convolution operation,that is,the multiplication and addition operation process,can be easily completed by the ESF3 memory device.In this paper,an ESF3 NOR Flash memory array model with a scale of 1024x512 is built,and each memory cell supports 3bit data storage.Based on VGG-16 Net,a new model is built to simulate and verify the performance of the CIM circuit.The method of over-half top value quantization is used to quantize the full-precision neural network into a limited-precision convolutional neural network.Based on 40 nm process,the design and simulation of multi-bit CIM peripheral circuits are completed.Based on the above design,this ESF3 NOR Flash CIM circuit supports 4-bit multiply-and-accumulate operations.When using the Cifar-10 data set for recognition and verification,it can achieve a recognition accuracy of 91.2%,and can achieve a system energy efficiency of 54.7TOPS/W.