| In the new era of information development,people’s demand for mobile communication has increased significantly,so the 5th generation mobile communication system(5G)has been rapidly developed in a short period of time,and 5G will play an increasingly important role in the future.5G has higher requirements on information transmission rate,reliability and delay,and channel coding technology is one of the main wireless transmission technologies to meet these requirements.Low density parity check(LDPC)codes have excellent performance close to the Shannon limit,and the inherent parallelism of iterative decoding schemes,which make LDPC decoders suitable for hardware implementation.Therefore,LDPC codes have been used as the data channel encoding scheme in 5G enhanced Mobile Broadband(e MBB)scenarios.Consequently,the theoretical and implementation research on 5G LDPC codes has received widespread attention.In this paper,the quantized MinSum(MS)algorithm of 5G LDPC codes and the hardware design of multirate compatible decoders are studied in detail.The main research work is as follows:In order to improve the performance loss of quantified MS decoding algorithms of 5G LDPC codes,a modified adapted Min-Sum(MAMS)decoding algorithm is presented.First,based on the fact that the decoding performance of 5G LDPC codes is more sensitive to the offset factor in the check-nodes update function when the row and column degrees of check matrix are low,different check-nodes update functions are adopted according to different values of row and column degrees to improve the error correction ability.Then,the third minimum amplitude of the messages passed from the variable nodes to a check node is introduced to adjust the offset factor to reduce the decoding error rate.Afterwards,by setting the threshold for the iteration number,check-nodes update functions of different complexity are used in the iteration process to reduce the complexity of the decoding algorithm.Finally,the performance simulation results show that the modified quantified decoding algorithm proposed in this thesis has better error correction ability and decoding performance.Aiming at the hardware implementation of 5G LDPC codes,the hardware design and implementation of multi-rate compatible codec are completed.First,in the design of codec,different parameter values in the process of information storage and information operation are compatible processing,and the entire cyclic shift factor coefficients of 5G standard are saved in the shift factor storage module,so as to realize the hardware compatibility of LDPC codes with different code lengths and code rates in 5G standard.Then,in the hardware implementation of the decoder,the data reading structure in the decoding process is optimized,that is,a new cyclic shift control module is used to reduce the use of the cyclic shift network,which reduces the decoding delay and hardware resource consumption of the decoder.Finally,the correctness of the design of multi-rate compatible codec of 5G LDPC codes is verified through the hardware simulation platform,and the design of the codec can effectively reduce the consumption of hardware resources. |