| As the core of my country’s modernization construction,the Internet is closely related to production and life.As the most efficient and flexible equipment in the backbone network,the network processor has been widely concerned and used.Based on this background,The subject of this paper comes from the major technical research projects of the national ministries and commissions.As the most efficient and flexible part of the backbone network,network processors can assist in cloud computing or act as routers and switches,and the flexibility of network processors depends on the "match-action" model.This paper firstly analyzes various architectures of the "match-action" model in network processors,according to the result I designed a packet Manipulator processor which is suitable for XDNP switching architecture by combining the very long instruction word architecture with the MMT model.Combining instruction processing and hardware co-processing,a packet header vector processing circuit with flexibility and efficiency coexisting is implemented.It has four processing cores,four output reorganization units,and a very long instruction FIFO and a CSR module.Each processing core has eight identical instruction pipelines,an input transfer unit and a register file.The processing core is used to complete the field processing function.The output reorganization unit is used to combine the processing result with the packet field.The very long instruction FIFO is used to cache the instructions of the matching-level search result,and the CSR module is used to increase the configurable function and flexibility,as well as counting statistics on incoming and outgoing traffic.Further,a number of custom microcode instructions are designed for the packet processing architecture.The main function of the instructions is to process data packets.In addition,supporting basic arithmetic and logic operations,it also includes Byte-based LOAD instructions and STORE instructions,and then I designed a very long instruction word format,which includes thirty-two 32 bits instructions and 4bits flag bits.According to the different processing requirements of the fields in the message,very long instruction sequences are designed based on this instruction set.The instruction sequences include basic action modification,replacement,addition,deletion,discarding,copying and counting operations,covering operations such as IEEE802.3,TCP/IP,ARP,and other basic protocols.Subsequently,based on the instruction set,a three-level instruction pipeline and a four-level instruction pipeline were successively designed.The performance of the two pipelines was simulated and analyzed,and the pipeline with the four-level as the packet Manipulator processor was finally determined.There are four stages of fetch,decode,execution and writing back in the pipeline which used a two-stage forwarding function to solve the data conflict in the pipeline and to ensure the correctness of processing.After that,the output reassembly unit is designed.When the pipeline executes the S_TYPE instruction,the reassembly unit will combine the processing result with the packet field according to the instruction.When the pipeline executes the NOP instruction,the reassembly unit will bypass the input packet header vector to the output.After that,I designed the CSR module,considering the generality of the packet Manipulator processor,it is designed to change its effective processing bit width by configuration,which can be applied to NP with different design requirements.Finally,the packet Manipulator processor was verified by high-level simulation and RTL simulation.Due to the custom instruction set in this design,the microcode instruction was used as the verification method of design.Verification revolves around operations such as modifying,replacing,adding,deleting,discarding,copying,and counting.During verification,specific function assembly instructions were artificially written,and then the microcode was read into the DUT after converted into a hexadecimal file by an encoder.When judging the results,firstly compare the flow counters at the input and output ends of the packet Manipulator processor to see if there is any packet loss,then perform high-level simulation,and comparing the results of the high-level simulation with the RTL simulation results.The results show the function implemented by the circuit as expected.Next,I designed coverage test points,which constrained the test vector with the test points,and used two methods of directional testing and random testing to conduct coverage analysis,and the results showed that the coverage converges.Subsequently,I used the XCVU13 P development board combined with the Spirent network protocol analyzer for board-level verification.The results showed that the packet Manipulator processor designed in this paper meets the design requirements of 40 Gbps at a clock frequency of 312.5MHz.Finally,the logic synthesis timing is closed of this design,and the consistency check is passed,under the condition of UMC28 nm. |
